Intel Corporation

Sherif R Sweha

Mark E Bauer

Peter K Hazen

Kevin W Frary

Rodney R Rozman

Sanjay S Talreja

Steven E Wells

Robert N Hasbun

Jahanshir J Javanifard

Duane R Mills

Mamun Ur Rashid

Richard D Pashley

Johnny Javanifard

Robert L Baltar

Sachidanandan Sambandan

Mark D Winston

David M Brown

Phillip M Kwong

George R Canepa

Phil Kliza

Steven D Pudar

Duane F Mills

George Blanchard

Glen Hawk

Gary J Gallagher

Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. &ldquo;By-output&rdquo; architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. &ldquo;By-address&rdquo; architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.

Bit map addressing schemes for flash memory

A method and circuitry are described that permit one to utilize a partially functional integrated circuit memory. A memory array is segregated into separate blocks that can each be isolated to minimize the amount of the memory array rendered unusable by a defect. Circuitry is also provided to program memory cells within the array to one of at least three amounts of charge and thereby increase the amount of storage provided by the remaining functional blocks.

Method and circuitry for usage of partially functional nonvolatile memory

Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. 'By-output' architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. 'By-address' architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.

Bit map addressing schemes for flash/memory

A nonvolatile memory includes a global line and a first block and a second block. The first block includes a plurality of first local lines and a first local decoder coupled to the global line and the first local lines for selectively coupling the global line to one of the first local lines in accordance with an address when the first local decoder is enabled and for isolating the first local lines from the global line when the first local decoder is disabled. The second block includes a plurality of second local lines and a second local decoder coupled to the global line and the second local lines for selectively coupling the global line to one of the second local lines in accordance with the address when the second local decoder is enabled and for isolating the second local lines from the global line when the second local decoder is disabled such that interference between the first and second blocks is eliminated during memory operations.

Nonvolatile memory blocking architecture

A nonvolatile memory device is described. The memory device includes a main memory array for storing data. The main memory array comprises a first block and a second block. A redundant memory array comprises a first redundant block and a second redundant block. The first redundant block comprises a first redundant column of memory cells and a second redundant column of memory cells. The second redundant block comprises a third redundant column of memory cells and a fourth redundant column of memory cells. A content addressable memory (CAM) comprises a first set of CAM cells for storing a first address of a first defective column in the main memory array and a second set of CAM cells for storing a second address of a second defective column in the main memory array. The first set of CAM cells cause the first redundant column in the first redundant block to replace the first defective column when the first defective column is in the first block. The first set of CAM cells cause the third redundant column in the second redundant block to replace the first defective column when the first defective column is in the second block. The second set of CAM cells cause the second redundant column in the first redundant block to replace the second defective column when the second defective column is in the first block. The second set of CAM cells cause the fourth redundant column in the second redundant block to replace the second defective column when the second defective column is in the second block.

Nonvolatile memory with blocked redundant columns and corresponding

A nonvolatile memory includes a first block and a second block. The first block comprises a first memory cell and a first source line coupled to a source of the first memory cell. The second block comprises a second memory cell and a second source line coupled to a source of the second memory cell. A first source switch is coupled to the first source line for selectively coupling a first potential, a second potential, and a third potential to the first source line. The second potential has a voltage intermediate between the first potential and the third potential. A second source switch is coupled to the second source line for selectively coupling one of the first, second, and third potentials to the second source line. A block select circuit receives a block address for selecting one of the first and second source switches to couple one of the first, second, and third potentials to its respective one of the first and second source lines. A configuration cell is coupled to the block select circuit for configuring block operations of the first and second blocks. When the configuration cell is in a first voltage state, the configuration cell causes the block select circuit to separately select one of the first and second source switches depending upon the address received. When the configuration cell is in a second voltage state, the configuration cell causes the block select circuit to collectively select the first and second source switches.

Floating gate nonvolatile memory with configurable erasure blocks

In a memory array in which logic signals of a first and a second voltage levels are used for selecting memory positions in the array for read operations and at least one signal of a voltage level higher than the first and second voltage levels may appear, and including a plurality of wordlines each joined to a common node by individual row decoders, a predecoder circuit for selecting a plurality of wordlines from which a row decoder may select an individual wordline including a full CMOS NAND gate arranged to provide output voltage levels of the first and a second voltage levels, a plurality of weak P channel devices each connected to one of the wordlines, means for operating the weak P channel devices to provide voltage levels of the higher level and below at the wordlines, means for limiting value of voltage transferred to the common point to be less than the higher voltage level, and means for limiting the level of the voltage transferred to the common node from the NAND gate to be less than a predetermined level.

High-speed tri-level decoder with dual-voltage isolation

A nonvolatile memory device residing on a substrate is described. The memory device includes a first block and a second block. The first block includes a first sub-block comprising a first memory cell, a first bit line coupled to a drain of the first memory cell, and a first source line coupled to a source of the first memory cell. The first block also includes a second sub-block which includes a second memory cell, a second bit line coupled to a drain of the second memory cell, and a second source line coupled to a source of the second memory cell. The second block comprises a third sub-block comprising a third memory cell, a third bit line coupled to a drain of the third memory cell, and a third source line coupled to a source of the third memory cell. The second block also includes a fourth sub-block which includes a fourth memory cell, a fourth bit line coupled to a drain of the fourth memory cell, and a fourth source line coupled to a source of the fourth memory cell. The first sub-block of the first block and the third sub-block of the second block are grouped together on the substrate to form a first data bit group corresponding to a first data pin of the memory device such that the distances of the first and third memory cells of the first data bit group to a first sensing circuit are substantially minimized and are substantially equal. The second sub-block of the first block and the fourth sub-block of the second block are grouped together on the substrate to form a second data bit group corresponding to a second data pin of the memory device such that the distances of the second and fourth memory cells of the second data bit group to a second sensing circuit are substantially minimized and are substantially equal.

Floating gate nonvolatile memory with distributed blocking feature

A memory device includes a memory array and a plurality of output pins. A control input is provided for receiving a control signal. The control signal can be in a first voltage state and a second voltage state. When the control signal is in the first voltage state, the memory device is in a first output mode. When the control signal is in the second voltage state, the memory device is in a second output mode. Circuitry is provided for selectively coupling the plurality of output pins to the memory array. An output mode select logic is coupled to receive the control signal for selecting the first output mode and the second output mode for the memory device. When the memory device is in the first output mode, the output mode select logic controls the circuitry to couple all of the plurality of output pins to the memory array. When the memory device is in the second output mode, the output mode select logic controls the circuitry to couple a portion of the plurality of output pins to the memory array. A method of controlling the memory device to switch between the first output mode and the second output mode is also described.

Memory device having selectable number of output pins

In a memory array having a plurality of bitlines each connected to a plurality of memory devices having a state in which current is transferred by the memory device and a state in which current is not transferred by the device, a column select device for activating each bitline, a plurality of wordlines for activating individual memory devices joined to each bitline, apparatus for providing constant current in the conducting state of a memory device connected to a bitline, a device connecting a source voltage to a plurality of bitlines, and a reference bitline for providing an output reference signal, the improvement including apparatus for providing a source of current in addition to current through the device connecting a source voltage to a plurality of bitlines in order to charge any capacitance of a selected bitline when that bitline is selected whereby switching between memory devices joined to different bitlines is accelerated.

Apparatus for increasing the speed of operation of non-volatile memory

A redundancy programming circuit employing a two EPROM cell CAM for storing programmed states of redundant elements. The CAMs are disposed aside a memory array and word lines of the array are extended to the CAMs for programming the CAMs. Two word lines are coupled to each EPROM cell so that programming can still be achieved in the event one of the lines is defective.

Growing community of inventors

El Dorado Hills, CA, United States of America

Sherif R Sweha