Texas Instruments Corporation

Nvidia Corporation

Sherif Embabi

Abdellatif Bellaouar

Francesco Dantoni

Samuel D Pritchett

Jeffrey A Schlang

Ahmed Reda Fridi

Alan R Holden

Frank Zhang

Sherif Abdelhalem

Michel Frechette

Wing Kan Chan

Ahmed N Mohieldin

Charles Gore, Jr

Mohamed A I Mostafa

Moderage C Fernando

Mohamed A Mostafa

A low noise amplifier includes a first input transistor coupled to an input signal and a second input transistor coupled to the input signal. The low noise amplifier also includes a first output transistor, coupled between the first input transistor and a first carrier aggregation load, configured to connect the first input transistor to the first carrier aggregation load. Additionally, the low noise amplifier includes a second output transistor, coupled between the first input transistor and a second carrier aggregation load, configured to connect the first input transistor to the second carrier aggregation load. Further, the low noise amplifier includes a third output transistor, coupled between the second input transistor and the second carrier aggregation load, configured to connect the second input transistor to the second carrier aggregation load. Also included are a method of operating a low noise amplifier and an extended carrier low noise amplifier.

Low noise amplifier architecture for carrier aggregation receivers

An RF receiver apparatus () is provided physically separately from a cooperating baseband processor apparatus (). The RF receiver includes a mixer circuit () and an analog IF-to-digital baseband converter () formed on an integrated circuit. Sampling frequencies of the analog IF-to-digital baseband converter are controlled by the RF receiver apparatus.

If-to-baseband conversion for flexible frequency planning capability

A subsampling receiver () for converting an RF signal to baseband is disclosed. The subsampling receiver () may be implemented into a wireless communications device (), such as a wireless telephone handset. In one disclosed embodiment, the receiver () includes a sample and hold circuit () that samples a bandpass filtered input modulated signal at the subsampling frequency (f) that is well below the RF carrier frequency but twice the bandwidth (BW) of the payload; the sampled signal is digitized, and applied to two digital mixers (I,Q) to produce in-phase and quadrature components (I,Q) of the payload. In another embodiment, the receiver () includes two sample and hold circuits (I,Q) to sample the filtered signal at different phases of the sampling frequency, to produce the in-phase and quadrature digital components. In a third embodiment, the receiver () includes an analog mixer () to downconvert the RF input to an intermediate frequency, prior to digitization and digital mixing at quadrature phase.

Subsampling RF receiver architecture

An integrated circuit (ICT) comprising a filter ( ). The filter comprises an input (&ugr; &plus;) for receiving an input signal and an output ( ) for producing an output signal having a frequency cutoff point. The filter further comprises at least one resistor network (RN ) coupled between the input and the output. The resistor network comprises a first non-switched resistance (R ) and a first resistance series connection connected in parallel with the first non-switched resistance. The first resistance series connection comprises a switched resistance (R ) connected in series with a source/drain path of a switching transistor (TRR ), the switching transistor having a gate for receiving a control signal. The frequency cutoff point is adjustable in response to the control signal. Additionally, the switched resistance has a first resistance and the switching transistor has an on-resistance. Further, the on-resistance is at least 20 percent of the total of the first resistance and the on-resistance.

High frequency tunable filter

A very fast lock integer N PLL with hybrid digital coarse VCO tuning and VCO temperature drift compensation provides for a fully digital tuning scheme without the need for charge pumps. A PLL synthesizer ( ) using such a PLL design provides for very fast lock times by using an open loop step and a closed loop step. The hybrid PLL can achieve coarse tuning within four clock cycles, while minimizing any errors caused by the VCO non-linearity. Temperature tracking and compensation is also provided. A SAR implementation ( ) and an interpolation tuning implementation ( ) are also described.

Method for tuning a VCO using a phase lock loop

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Plano, TX, United States of America

Sherif Embabi