Qualcomm Incorporated

Nvidia Corporation

Sherif Abdelhalem

Hasnain Lakdawala

Bassel Hanafi

Abdellatif Bellaouar

William James Biederman

Li-chung Chang

Ahmed A Youssef

Ehab Abdel Ghany

Frank Zhang

Sherif Embabi

Li-Chung Chang

Iii William James Biederman

Ehab A Abdel Ghany

Certain aspects of the present disclosure generally relate to a multi-output amplifier implemented using a capacitive attenuator. For example, the multi-output amplifier generally includes a first capacitive attenuator coupled to an input node of the multi-output amplifier. In certain aspects, the multi-output amplifier also includes a first amplification stage having an input coupled to a tap node of the first capacitive attenuator and an output coupled to a first output node of the multi-output amplifier, and a second amplification stage having an output coupled to a second output node of the multi-output amplifier. For certain aspects, the multi-output amplifier includes a second capacitive attenuator coupled to the input node of the multi-output amplifier, and the second amplification stage may have an input coupled to a tap node of the second capacitive attenuator.

Low-noise amplifier (LNA) with capacitive attenuator

A low noise amplifier includes a first input transistor coupled to an input signal and a second input transistor coupled to the input signal. The low noise amplifier also includes a first output transistor, coupled between the first input transistor and a first carrier aggregation load, configured to connect the first input transistor to the first carrier aggregation load. Additionally, the low noise amplifier includes a second output transistor, coupled between the first input transistor and a second carrier aggregation load, configured to connect the first input transistor to the second carrier aggregation load. Further, the low noise amplifier includes a third output transistor, coupled between the second input transistor and the second carrier aggregation load, configured to connect the second input transistor to the second carrier aggregation load. Also included are a method of operating a low noise amplifier and an extended carrier low noise amplifier.

Low noise amplifier architecture for carrier aggregation receivers

A device and method for amplifying signals is provided. The device can have an input to receive an input signal having a first desired signal on a first carrier, a second desired signal on a second carrier, and one or more interfering signals. The device can have a first carrier aggregation (CA) chain for use with the first desired signal and a second CA chain for use with the second desired signal. The first and second CA chains can be coupled to the input. The first and second CA chains can have a plurality of transconductance stages. Each of the transconductance stages can be configured as a high impedance stage or a low impedance stage. The transconductance stages can be selectively activated to incrementally adjust the transconductance, and therefore the input impedance, of each of the CA chains.

Wideband high linearity LNA with intra-band carrier aggregation support

Amplifiers with inductive degeneration and configurable gain and input matching are disclosed. In an exemplary design, an apparatus includes a gain transistor, an inductor, and an input matching circuit for an amplifier. The gain transistor has a variable gain determined based on its bias current. The inductor is coupled between the gain transistor and circuit ground. The input matching circuit is selectively coupled to the gain transistor based on the variable gain of the gain transistor. For example, the input matching circuit may be coupled to the gain transistor in a low-gain mode and decoupled from the gain transistor in the high-gain mode. In an exemplary design, the input matching circuit includes a resistor, a capacitor, and a second transistor coupled in series. The resistor is used for input matching of the amplifier. The second transistor couples or decouples the resistor to or from the gain transistor.

Amplifiers with inductive degeneration and configurable gain and input matching

Amplifiers with improved isolation are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes an amplifier having a gain transistor, first and second cascode transistors, and a shunt transistor. The gain transistor receives an input signal and provides an amplified signal. The first cascode transistor is coupled between the gain transistor and an intermediate node and receives the amplified signal. The second cascode transistor is coupled between the intermediate node and an output node and provides an output signal. The shunt transistor is coupled between the intermediate node and circuit ground. The first and second cascode transistors are enabled to provide the output signal. The shunt transistor is (i) disabled when the cascode transistors are enabled and (ii) enabled to short the intermediate node to circuit ground when the cascode transistors are disabled.

Amplifiers with improved isolation

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San Diego, CA, United States of America

Sherif Abdelhalem