Spansion Llc.

Cypress Semiconductor Corporation

Advanced Micro Devices Corporation

Monterey Research, LLC

Infineon Technologies LLC

Globalfoundries Inc.

Spanion LLC

Shenqing Fang

Chun Chen

Kuo-Tung Chang

Youseok Suh

Kuo Tung Chang

Mark T Ramsbey

Angela Tai Hui

Unsoon Kim

Sameer S Haddad

Wenmei Li

Gang Xue

Scott Allan Bell

Meng Ding

Tung-Sheng Chen

Hidehiko Shiraiwa

Inkuk Kang

James Minsu Pak

Tim Thurgate

Fei Wang

Hiroyuki Ogawa

Yu Nan Sun

Zhigang Wang

Michael Allen Van Buskirk

Yi Ma

Lei Xue

Ming Sang Kwan

Rinji Sugino

Amol Ramesh Joshi

David H Matsumoto

Kazuhiro Mizutani

Pavel Fastenko

Timothy J Thurgate

Chih-Yuh Yang

Alexander H Nickel

Jihwan Choi

Lovejeet Singh

Calvin T Gabriel

Hiroyuki Kinoshita

Robert B Ogle

Connie P Wang

Yoram Betser

Allison Holbrook

Wen Yu

Harpreet Kaur Sachar

Shivananda Shetty

Amichai Givant

Wai Lo

Kelwin Ko

Eunha Kim

Mark S Chang

Kashmir S Sahota

Connie Pin-Chin Wang

Minh-Van Ngo

Phillip Lawrence Jones

Hyesook Hong

Zubin Patel

Hapreet Sachar

Nian Niles Yang

Richard M Fastow

Chi K Chang

Ning Cheng

Takashi Whitney Orimoto

Jean Y Yang

Joong Jeon

Chungho Lee

Satoshi Torii

Huaqiang Wu

Yukio Hayakawa

Di Li

Jayendra D Bhakta

Hiroyuki Nansei

Minghao Shen

Fred Cheung

Takayuki Maruyama

Christie R K Marrian

Scott Bell

Shao-Yu Ting

Jeremy Wahl

Disclosed herein is a semiconductor device comprising a first dielectric disposed over a channel region of a transistor formed in a substrate and a gate disposed over the first dielectric. The semiconductor device further includes a second dielectric disposed vertically, substantially perpendicular to the substrate, at an edge of the gate, and a spacer disposed proximate to the second dielectric. The spacer includes a cross-section with a perimeter that includes a top curved portion and a vertical portion substantially perpendicular to the substrate. The perimeter further includes a discontinuity at an interface of the top curved portion with the vertical portion. Further, disclosed herein are methods associated with the fabrication of the aforementioned semiconductor device.

Method of spacer formation with straight sidewall of memory cells

A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate and further disposing a cap layer over the gate layer. A first transistor gate is defined having an initial thickness substantially equal to a combined thickness of the cap layer and the gate layer. A first doped region is formed in the substrate adjacent to the first transistor gate. The cap layer is subsequently removed and a second transistor gate is defined having a thickness substantially equal to the thickness of the gate layer. Afterwards, a second doped region is formed in the substrate adjacent to the second transistor gate. The first doped region extends deeper in the substrate than the second doped region, and a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate.

Split gate charge trapping memory cells having different select gate and memory gate heights

A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.

Memory first process flow and device

A semiconductor device having a substrate, a dielectric layer, a polycrystalline silicon ('poly') resistor, a drain, and a source is disclosed. After implantation, the poly resistor may have a lateral doping profile with two peaks, one near each edge of the poly resistor, and a trough near the middle of the poly resistor. Such a doping profile can allow the poly resistor to have a resistance that is insensitive to small variations in critical dimension of the poly resistor. The resistance of the poly resistor may be determined by the doping dose of the tilted implant used to form the poly resistor. The tilted implant may be used to form the drain and the source of a transistor substantially simultaneously as forming the poly resistor.

Tilted implant for poly resistors

A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the core cells by the first component. The first component includes a wordline separated from the channel by a stack of layers including a charge trapping layer, and a distance between the wordline of the first component and the wordline of a first core cell in the plurality of core cells is substantially the same as distances between each wordline in the plurality of word core cells.

NAND memory cell string having a stacked select gate structure and process for forming same

A method to fabricate a non-planar memory device including forming a multi-layer silicon nitride structure substantially perpendicular to a top surface of the substrate. There may be multiple non-stoichiometric silicon nitride layers, each including a different or same silicon richness value from one another.

Varied silicon richness silicon nitride formation

A split gate device that includes a memory gate and a select gate disposed side by side, a dielectric structure having a first portion disposed between the memory gate and a substrate and a second portion disposed along an inner sidewall of the select gate to separate the select gate from the memory gate, and a spacer formed over the select gate along an inner sidewall of the memory gate. Other embodiments of embedded split gate devices including high voltage and low voltage transistors are also disclosed.

Charge trapping split gate device and method of fabricating same

At integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes.

Memory device interconnects and method of manufacture

An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes.

A semiconductor device that has a split gate charge trapping memory cell having select and memory gates of different heights is presented herein. In an embodiment, the semiconductor device also has a low voltage transistor and a high voltage transistor. In one embodiment, the gates of the transistors are the same height as the select gate. In another embodiment, the gates of the transistors are the same height as the memory gate.

NAND memory cell string having a stacked select gate structure and process for for forming same

A memory device that has a first gate disposed adjacent to a second gate and a first dielectric structure disposed between the first and second gates. The first dielectric structure has at least four layers of oxide and nitride films arranged in an alternating layer, in which each of the at least four or more layers includes a width in an approximate range of 30 &#x212b; or less. The first dielectric structure further includes a top surface that is substantially un-etched.

Multi-layer inter-gate dielectric structure and method of manufacturing thereof

A structure and method for providing improved and reliable charge trapping memory device are disclosed herein. A charge trapping field effect transistor (FET) comprising a semiconductor substrate, a doped region in the semiconductor substrate, and a gate structure on the semiconductor substrate and a method of fabricating the same are also discussed. The doped region comprises a first lateral dimension along a first direction. The gate structure comprises a charge trapping dielectric region and a charge trapping conductive region in contact with the charge trapping dielectric region.

Charge-trapping memory device

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Fremont, CA, United States of America

Shenqing Fang