Shanghai Cambricon Information Technology Co., Ltd

Cambricon (xi'an) Semiconductor Co., Ltd.

Cambricon Technologies Corporation Limited

Shengyuan Zhou

Tianshi Chen

Zidong Du

Shaoli Liu

Qi Guo

Zai Wang

Shuai Hu

Yao Zhang

Bingrui Wang

Tian Zhi

Xuda Zhou

Zhou Fang

Xishan Zhang

Jie Wei

Yuzhe Luo

Qun Liu

Wei Li

There is provides an operation module, which includes a memory, a register unit, a dependency relationship processing unit, an operation unit, and a control unit. The memory is configured to store a vector, the register unit is configured to store an extension instruction, and the control unit is configured to acquire and parse the extension instruction, so as to obtain a first operation instruction and a second operation instruction. An execution sequence of the first operation instruction and the second operation instruction can be determined, and an input vector of the first operation instruction can be read from the memory. The operation unit is configured to convert an expression mode of the input data index of the first operation instruction and to screen data, and to execute the first and second operation instruction according to the execution sequence, so as to obtain an extension instruction.

Operation module and method thereof

A computing device, comprising: a computing module, comprising one or more computing units; and a control module, comprising a computing control unit, and used for controlling shutdown of the computing unit of the computing module according to a determining condition. Also provided is a computing method. The computing device and method have the advantages of low power consumption and high flexibility, and can be combined with the upgrading mode of software, thereby further increasing the computing speed, reducing the computing amount, and reducing the computing power consumption of an accelerator.

Sparse training in neural networks

The present disclosure provides a signal processing device, including a signal collector, an instruction converter, and a processor. Examples of the present disclosure may achieve precise recognition of users' intentions and bring operational conveniences to users.

Signal processing device and related products

The disclosure provides a task segmentation device and method, a task processing device and method, a multi-core processor. The task segmentation device includes a granularity task segmentation unit configured to segment a task by adopting at least one granularity to form subtasks, and a task segmentation granularity selection unit configured to select the granularity to be adopted.

Data sharing system and data sharing method therefor

Apparatus and method for sparse training acceleration in neural networks

Computing device and method

The present disclosure relates to a processing device including a memory configured to store data to be computed; a computational circuit configured to compute the data to be computed, which includes performing acceleration computations on the data to be computed by using an adder circuit and a multiplier circuit; and a control circuit configured to control the memory and the computational circuit, which includes performing acceleration computations according to the data to be computed. The present disclosure may have high flexibility, good configurability, fast computational speed, low power consumption, and other features.

Processing apparatus and processing method

A processing device with dynamically configurable operation bit width, characterized by comprising: a memory for storing data, the data comprising data to be operated, intermediate operation result, final operation result, and data to be buffered in a neural network; a data width adjustment circuit for adjusting the width of the data to be operated, the intermediate operation result, the final operation result, and/or the data to be buffered; an operation circuit for operating the data to be operated, including performing operation on data to be operated of different bit widths by using an adder circuit and a multiplier; and a control circuit for controlling the memory, the data width adjustment circuit and the operation circuit. The device of the present disclosure can have the advantages of strong flexibility, high configurability, fast operation speed, low power consumption or the like.

Processing apparatus and processing method with dynamically configurable operation bit width

The present disclosure relates to a fused vector multiplier for computing an inner product between vectors, where vectors to be computed are a multiplier number vector {right arrow over (A)}{AN . . . A2A1A0} and a multiplicand number {right arrow over (B)} {BN . . . B2B1B0}, {right arrow over (A)} and {right arrow over (B)} have the same dimension which is N+1. The multiplier includes: N+1 multiplication sub-units configured to perform multiplication on each dimension of a vector respectively, and take lower n bits of the multiplier number vector for multiplication each time, where the n bits are removed from the binary number of each dimension of the multiplier number vector after the n bits are taken, and n is larger than 1 and less than N+1; an adder tree configured to perform addition on results of N+1 multiplication sub-units obtained from a same operation each time; and a result register configured to hold a result of every addition performed by the adder tree and send the result to the adder tree for next computation.

The disclosure provides a data processing device and method. The data processing device may include: a task configuration information storage unit and a task queue configuration unit. The task configuration information storage unit is configured to store configuration information of tasks. The task queue configuration unit is configured to configure a task queue according to the configuration information stored in the task configuration information storage unit. According to the disclosure, a task queue may be configured according to the configuration information.

Data processing apparatus and method

A data sharing system may include a storage module and at least two processing modules. The at least two processing modules may share the storage module and the at least two processing modules communicate to implement data sharing. A data sharing method for the data sharing system is provided. According to the disclosure, a storage communication overhead may be reduced, and a data access delay may be effectively reduced.

Growing community of inventors

Pudong New Area, China

Shengyuan Zhou