Integrated Device Technology, Inc.

Parade Technologies, Ltd.

Shengyuan Zhang

Shoujun Wang

Hongquan Wang

Yong Wang

Kochung Lee

Liang Xu

Yuanping Chen

Yu Zhang

Mengchuan Gao

Qing Chen

Yunfu Yang

Jianhong Li

This application is directed to controlling a low power mode of a data communication channel. An electronic device includes an input interface for receiving an input signal. A signal conditioning circuit is coupled to the input interface, and configured to be disabled and consume power below a first threshold power level in a low power mode. A first signal detector is coupled to the signal conditioning circuit, and a second signal detector is coupled to the first signal detector. The first signal detector is configured to monitor a differential mode component of the input signal for controlling the signal conditioning circuit to exit the low power mode. The second signal detector is configured to, in the low power mode, detect a start of the input signal and enable the first signal detector based on a common mode component of the input signal.

Exiting of low power modes of redrivers and retimers

This application is directed to a data interface having an input interface for receiving a differential input signal and a reference interface for providing a predefined reference voltage. A high pass filter is coupled to the input interface, and configured to filter the differential input signal and generate a filtered differential input signal. A differential integrator is coupled to the high pass filter and reference interface, and configured to receive the filtered differential input signal and generate a differential output signal including a first output signal and a second output signal. Each of the first and second output signals has a common mode output voltage substantially equal to the predefined reference voltage. In some embodiments, the data interface includes a connector including a plurality of data lanes and a pair of command pins that are distinct from the data lanes and coupled to the input interface.

Receiver circuit with automatic DC offset cancellation in display port applications

A method and circuit for generating an adjustable delay signal is presented, wherein the delay can be linear and monotonic with high resolution delay steps. The circuit utilizes one or more serially coupled delay cells and a load cell. Each delay cell comprises an inverter, a nor-multiplexer, and a programmable capacitor, wherein a first control signal is used to control the operation of the nor-multiplexer and a second control signal is used to control capacitance of the programmable capacitor. Values of the first and the second control signals are selected based on any desired range of total delay time and any desired delay time for a specific application of the circuit.

Linear monotonic delay chain circuit

Switching and repeating applications using an impedance matched source follower improve performance of high speed links such as PCI Express, HDMI, DisplayPort and DVI by reducing attenuation and other degradation of high speed signals, including those with transmit pre-emphasis, by avoiding impedance discontinuities over process, voltage and temperature variations and by driving a broader range of loads, e.g., heavily capacitive loads. A circuit for switching or repeating signals on a single-ended or differential high speed link may comprise a source follower with input and output impedances matched to input and output transmission lines on the high speed link. The source follower is biased by a constant transconductance circuit, an external calibration circuit or other circuit to provide an essentially constant output impedance over process, voltage and temperature variations.

Low-loss impedance-matched source-follower for repeating or switching signals on a high speed link

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Shanghai, China

Shengyuan Zhang