Oak Technology, Inc.

Other

Shengquan Wu

Kevin Chiang

Phares J Grey

Jhy-Ping Shaw

Li-Huan Jen

Scott Li-Huan Jen

Method and system for compensating for a segment length of one or more of three consecutive mark and space segments utilized in a computer system. The three segments are received at a first pre-processor, the first segment is separated and issued separately from the remaining two segments, and the first segment length is compared with a permitted range of lengths. If the first segment length is not within the permitted range, a first error signal is issued, preferably indicating the non-complying first length. This process is repeated at second and third pre-processors. A segment processor receives the three individual segments and the error signals and non-complying lengths, if any, and compensates or corrects for any non-complying segment lengths before further processing occurs.

Pattern detection for computer segments

Method and system for determining varying widths of each of a sequence of signal components (marks and spaces) in an incoming digital signal stream and for indicating which mark widths and which space widths fall outside acceptable ranges. A pre-mark and pre-space are added to the front end of the recieved stream for alignment purposes. The width of each signal component (mark or space) is determined and compared with an acceptable range of mark widths or space widths. Each mark or space that lies outside an acceptable range has an indicium associated with this mark or space, indicating this non-compliance. The modified digital signal stream, including the indicia, is re-issued after a selected time delay for subsequent signal processing. A method for measurement or estimation of mark width and space width is presented.

Detection of EFM stream component widths

A method for set-up of a group of parameter values needed in a CD-R or CD-RW write cycle, where the time allotted for set-up is as low as six clock cycles. In a clock cycle from a preceding write cycle, first and second parameter values are read into first and second registers, and a third parameter value is read into a first SRAM. In clock cycles 1-5 of the present write cycle, fourth, fifth, sixth, seventh and eighth parameter values are read into second, third, fourth, fifth and sixth SRAMs. In clock cycle no. 6 or later of the present write cycle, three sums (or differences) of selected combinations of these eight parameter values are calculated and stored, new first and second parameter values are read into first and second registers, and a new third parameter value is read into another SRAM. The method is generalized to K parameters stored in registers, N parameters stored in SRAMs and calculation of M selected linear combinations of the K&plus;N parameter values.

Write strategy and timing

A circuit records data on an optical disk while the disk is rotated at a constant angular velocity. A velocity detector determines a velocity of a rotating disk as a detected velocity. A memory stores sets of write signal control values, and each set of write signal control values is associated with a predefined velocity. A control circuit retrieves at least two sets of write signal control values based on the detected velocity and selected predefined velocities of the sets of write signal control values. A write strategy circuit generates one or more write signals in accordance with the write signal control values of the selected set and write data. The control circuit designates a selected set of write signal control values from the at least two sets of write signal control values while generating the one or more write signals.

Method and apparatus for writing data in a disk drive

Two banks of memory are selectively accessed from a first interface terminal and a second interface terminal through multiplexer circuitry whereby one memory bank can be read by one terminal while the other memory bank is being updated from the other interface terminal. The multiplexer circuitry is controlled by a control register which responds to an operation code whereby either memory bank can be updated while the other memory bank is being read for hardware parameters, for example.

Selectively accessible memory banks for operating in alternately reading or writing modes of operation

Under current CD-R and CD-RW technology, whenever a present mark is burned onto a CD, only the dimension of the present mark is considered in controlling the heat source (e.g. a laser). The present invention improves upon the current technology by taking into account not only the dimension of the present mark but also the effects on the present mark due to the marks and spaces within relatively close proximity to the present mark. By doing so, the present invention significantly improves the accuracy of the writing process. This in turn enables the present invention to eliminate the writing errors of the prior art.

Method and apparatus for controlling the writing of information onto a storage medium

A circuit and method for selectively and dynamically delaying a signal is presented. A series of delay modules are used to provide progressively finer delays. A multiplexer is used after each delay module to select one of a plurality of signals to pass on to a subsequent delay module. Each multiplexer is controlled by a control signal which can vary in time so that different delays can be selected for different portions of the signal to be delayed. By providing the proper control signals to the multiplexers any delay corresponding to a sum of the available individual delays generated by the individual delay modules is possible. The circuit and method are particularly useful for imposing individual delay times on the pulses in a logic level signal.

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Sunnyvale, CA, United States of America

Shengquan Wu