Qualcomm Incorporated

Shengqiong Xie

Chun-Chen Liu

Ju-Yi Lu

Integrated circuits and methods of manufacturing such circuits are disclosed herein that feature metal line-via matrix insertion after place and route processes are performed and/or completed for the integrated circuit's layout. The metal line-via matrix consists of one or more additional metal lines and one or more additional vias that are inserted into the integrated circuit's layout at a specific point to lower the current and current density through a first conductive path that has been determined to suffer from electromigration, IR-voltage drop, and/or jitter. Specifically, the metal line-via matrix provides one or more auxiliary conductive paths to divert and carry a portion of the current that would otherwise flow through the first conductive path. This mitigates electromigration issues and IR-voltage drop along the first conductive path. It may also help alleviate problems due to jitter along the path.

Mitigating electromigration, in-rush current effects, IR-voltage drop, and jitter through metal line and via matrix insertion

Various features pertain to circuit design schemes that route wires based on temperature. In one aspect, time-variant temperature conditions along a prospective route are taken into account when determining whether to use the route for a wire. For example, a route can be selected from among a set of prospective two-dimensional (2-D) or three-dimensional (3-D) routes based on which route is associated with the 'smoothest' temperature gradient. Other aspects of the disclosure pertain to determining or exploiting adjustable search windows, layer wiring densities, worst-case skew values and resistance-capacitance (RC) coupling characteristics, particularly for use with 3-D routing within the layers of a stacked multi-layer substrate.

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San Diego, CA, United States of America

Shengqiong Xie