Advanced Micro Devices Corporation

Spansion Llc.

Shengnian Davis Song

Sey-Ping Sun

Mark I Gardner

Bradley Marc Davis

Robert Louis Dawson

Joseph William Wiseman

Kelley Kyle Higgins

Bradley Davis

Methods and structures are provided for a dual-bit EEPROM semiconductor device. The dual-bit memory device comprises a semiconductor substrate, a tunnel oxide disposed on the semiconductor substrate and first and second spaced apart floating gates that are disposed on the tunnel oxide. An interlayer dielectric layer contacts the tunnel oxide layer at a position between the first and second spaced apart floating gates and electrically isolates the first and second spaced apart floating gates. A control gate contacts the interlayer dielectric layer between the first and second spaced apart floating gates.

Semiconductor memory devices and methods for fabricating the same

Various methods of inspecting a workpiece for residue are provided. In one aspect, a method of fabricating a conductor layer on a substrate is provided that includes forming an aluminum-copper film on the substrate in a first processing chamber and forming an anti-reflective coating on the aluminum-copper film in a second processing chamber. The substrate is moved from the second processing chamber into a cooling chamber to quench the substrate. A first time interval during which the substrate is in the first processing chamber and second time interval during which the substrate is present in the second processing chamber are measured. The substrate is annealed to restore a uniform equilibrium distribution of copper in the aluminum if the first time interval exceeds about 600 seconds or the second time interval exceeds about 300 seconds. The method substantially reduces the risk of metal comb bridging device failures following etch definition of conductor lines.

Method of fabricating conductor structures with metal comb bridging avoidance

A fabrication process for semiconductor devices is disclosed for forming ultra-thin gate oxides, whereby a silicon substrate is subjected to an N,O plasma to form the ultra-thin gate oxide. According to one embodiment, the silicon substrate is heated in a deposition chamber and the N,O plasma is created by applying RF power to a showerhead from which the N,O is dispensed. By reacting an N,O plasma directly with the silicon substrate it is possible to achieve gate oxides with thicknesses less than 20 &angst; and relative uniformities of less than 1% standard deviation. The oxide growth rate resulting from the presently disclosed N,O plasma treatment is much slower than other known oxide formation techniques. One advantage of the disclosed N,O plasma treatment over thermal oxidation lies in the predictability of oxide growth thickness resulting from reaction with N,O plasma versus the strong variation in oxide formation rates exhibited by thermal oxidation. Following gate oxide formation, a high temperature anneal may be performed, preferably in an RTA apparatus. By combining the N,O plasma treatment with an RTA process, the disclosed method is believed to offer a controllable and reproducible method for fabricating highly uniform, ultra-thin gate oxides, having low trapping state densities.

Ultra-thin gate oxide formation using an N2O plasma

A method is provided for determining the temperature of a semiconductor fabrication process in which a resistivity versus temperature calibration curve for a superlattice structure is created. A plurality of similar superlattice structures which include alternating layers of a conductor and a semiconductor may be annealed at different temperatures. The resistivity of each superlattice structure may then be measured after the superlattice structures have been cooled to room temperature in order to form the calibration curve. A similar superlattice structure may then be subjected to the temperature at which the semiconductor fabrication process is typically performed, causing the resistivity of the superlattice structure to change. Based on the resulting resistivity of the superlattice structure, the calibration curve may be used to determine the process temperature of the superlattice structure during the fabrication process. The length of time that the superlattice structure is subjected to the process temperature is selected to be the time duration of the process whose temperature is being determined. Once the actual process temperature is known, the temperature controls for the process may be adjusted in an attempt to reach the desired process temperature.

Using a superlattice to determine the temperature of a semiconductor fabrication process

Various methods of fabricating a circuit structure utilizing silicon nitride are provided. In one aspect, a method of fabricating a circuit structure is provided that includes forming a silicon nitride film on a silicon surface, annealing the silicon nitride film in an ammonia ambient and annealing the silicon nitride film in a nitrous oxide ambient to form a thin oxide layer at an interface between the silicon nitride film and the silicon surface. The process of the present invention enables the manufacture of thin silicon nitride films with highly uniform morphology for use as gate dielectrics or other purposes. The thin oxide film is self-limiting in thickness and improves differential mechanical stresses.

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Austin, TX, United States of America

Shengnian Davis Song