Southeast University

Csmc Technologies Fab2 Co., Ltd.

Shengli Lu

Weifeng Sun

Longxing Shi

Siyang Liu

Shen Xu

Qinsong Qian

Jing Zhu

Jiaxing Wei

Sheng Li

Chi Zhang

Kui Xiao

Miao Yang

Youshan Jin

Sichao Liu

Haisong Li

Chong Wang

Yangbo Yi

Guipeng Sun

Long Zhang

Chao Liu

Qi Liu

Dejin Wang

Hao Liu

Cheng Huang

Feng Lin

Shengyou Xu

Li Lu

Wei Pang

Rongcheng Lou

Yingbo Fan

Ruili Wu

Changlong Huo

Xianguo Huang

Ning Wang

Xianjun Fan

Kuo Yu

Yunwu Zhang

Lizhi Tang

Ankang Li

A heterojunction semiconductor device with a low on-resistance includes a metal drain electrode, a substrate, and a buffer layer. A current blocking layer is arranged in the buffer layer, a gate structure is arranged on the buffer layer, and the gate structure comprises a metal gate electrode, GaN pillars and AlGaN layers, wherein a metal source electrode is arranged above the metal gate electrode; and the current blocking layer comprises multiple levels of current blocking layers, the centers of symmetry of the layers are collinear, and annular inner openings of the current blocking layers at all levels gradually become smaller from top to bottom. The AlGaN layers and the GaN pillars are distributed in a honeycomb above the buffer layer.

Heterojunction semiconductor device with low on-resistance

A power semiconductor device includes: a substrate; drain metal; a drift region; a base region; a gate structure; a first conductive type doped region contacting the base region on the side of the base region distant from the gate structure; a source region provided in the base region and between the first conductive type doped region and the gate structure; contact metal that is provided on the first conductive type doped region and forms a contact barrier having rectifying characteristics together with the first conductive type doped region below; and source metal wrapping the contact metal and contacting the source region.

Power semiconductor device and manufacturing method therefor

A deep neural network hardware accelerator comprises: an AXI-4 bus interface, an input cache area, an output cache area, a weighting cache area, a weighting index cache area, an encoding module, a configurable state controller module, and a PE array. The input cache area and the output cache area are designed as a line cache structure; an encoder encodes weightings according to an ordered quantization set, the quantization set storing the possible value of the absolute value of all of the weightings after quantization. During the calculation of the accelerator, the PE unit reads data from the input cache area and the weighting index cache area to perform shift calculation, and sends the calculation result to the output cache area. The accelerator uses shift operations to replace floating point multiplication operations, reducing the requirements for computing resources, storage resources, and communication bandwidth, and increasing the calculation efficiency of the accelerator.

Deep neural network hardware accelerator based on power exponential quantization

A lateral insulated gate bipolar transistor (IGBT) with a low turn-on overshoot current is provided to reduce a peak value of a current flowing through a device during turn-on of a second gate pulse while preventing a current capability and a withstand voltage capability from being degraded. The lateral IGBT includes: a buried oxygen arranged on a P-type substrate, an N-type drift region arranged on the buried oxygen, on which a P-type body region and an N-type buffer region are arranged, a P-type collector region arranged in the N-type buffer region, a field oxide layer arranged above the N-type drift region, a P-type well region arranged in the P-type body region, and a P-type emitter region and an emitter region arranged in the P-type well region, where inner boundaries of the foregoing 4 regions are synchronously recessed to form a pinch-off region. A gate oxide layer is arranged on a surface of the P-type body region, and a polysilicon gate is arranged on the gate oxide layer. The polysilicon gate includes a first gate located above the surface of the P-type body region and a second gate located above the pinch-off region and the N-type drift region. The first gate is connected to a first gate resistor, and the second gate is connected to a second gate resistor.

Lateral insulated gate bipolar transistor with low turn-on overshoot current

The invention provides a graphene channel silicon carbide power semiconductor transistor, and its cellular structure thereof. Characterized in that, a graphene strip serving as a channel is embedded in a surface of the P-type body region and two ends of the graphene strip are respectively contacted with a boundary between the N+-type source region and the P-type body region and a boundary between the P-type body region and the N-type drift region, and the graphene strip is distributed in a cellular manner in a gate width direction, a conducting channel of a device is still made of graphene; in the case of maintaining basically invariable on-resistance and current transmission capacity, the P-type body regions are separated by the graphene strip, thus enhancing a function of assisting depletion, which further reduces an overall off-state leakage current of the device, and improves a breakdown voltage.

Graphene channel silicon carbide power semiconductor transistor

The invention discloses a self-adaptive synchronous rectification control system and a self-adaptive synchronous rectification control method of an active clamp flyback converter. The control system comprises a sampling and signal processing circuit, a control circuit with a microcontroller as a core and a gate driver. According to the control method, a switching-on state, an early switching-off state, a late switching-off state and an exact switching-off state of a secondary synchronous rectifier of the active clamp flyback converter can be directly detected, and the synchronous rectifier and a switching-on time of the synchronous rectifier in next cycle can be controlled according to a detection result. After several cycles of self-adaptive control, the synchronous rectifier enters the exact switching-on state, thus avoiding oscillation of an output waveform of the active clamp flyback converter.

Self-adaptive synchronous rectification control system and method of active clamp flyback converter

Parasitic high-voltage diodes implemented by integration technology in a high-voltage level shift circuit are used for charging a bootstrap capacitor C, wherein a power supply end of the high voltage level shift circuit is a high-side floating power supply VB, and a reference ground is a floating voltage PGD that is controlled by a bootstrap control circuit. A first parasitic diode Dand a second parasitic diode Dare provided between the VB and the PGD. The bootstrap control circuit is controlled by a high-side signal and a low-side signal.

Integrated bootstrap high-voltage driver chip and technological structure thereof

A control method for improving dynamic response of switch power is based on a closed-loop control system comprising a sampling module, a dynamic control module, an error calculation module, a PID module, a mode control module, and a PWM module. The sampling module samples an output voltage Vo, and the dynamic control module compares the output voltage Vo with a set maximum voltage Vomax, a set minimum voltage Vomin, and a reference voltage Vref, so as to determine whether to adopt a dynamic mode. In the dynamic mode, when the output voltage Vo changes greatly, the output voltage Vo is rapidly restored to a stable voltage by inputting large power or small power.

Control method for improving dynamic response of switch power

A power module of a square flat pin-free packaging structure for suppressing the power module from being excessively high in local temperature. The power module includes an insulating resin, a driving chip, a plurality of power chips, and a plurality of metal electrode contacts. The driving chip, the power chips, and the metal electrode contacts are electrically connected through a metal lead according to a predetermined circuit. A plurality of metal heat dissipating disks used for heat dissipation of the power chips and a driving chip lead frame are disposed at the bottom of the insulating resin. A plurality of metal power chip lead frames are disposed on the metal heat dissipating disks, the power chips are disposed on the power chip lead frames, and the drain electrodes of the power chips are electrically connected to the metal heat dissipating disks.

Power module of square flat pin-free packaging structure

A transverse ultra-thin insulated gate bipolar transistor having current density includes: a P substrate, where the P substrate is provided with a buried oxide layer thereon, the buried oxide layer is provided with an N epitaxial layer thereon, the N epitaxial layer is provided with an N well region and P base region therein, the P base region is provided with a first P contact region and an N source region therein, the N well region is provided with an N buffer region therein, the N well region is provided with a field oxide layer thereon, the N buffer region is provided with a P drain region therein, the N epitaxial layer is provided therein with a P base region array including a P annular base region, the P base region array is located between the N well region and the P base region, the P annular base region is provided with a second P contact region and an N annular source region therein, and the second P contact region is located in the N annular source region. The present invention greatly increases current density of a transverse ultra-thin insulated gate bipolar transistor, thus significantly improving the performance of an intelligent power module.

Transverse ultra-thin insulated gate bipolar transistor having high current density

A high-current, N-type silicon-on-insulator lateral insulated-gate bipolar transistor, including: a P-type substrate, a buried-oxide layer disposed on the P-type substrate, an N-type epitaxial layer disposed on the oxide layer, and an N-type buffer trap region. A P-type body region and an N-type central buffer trap region are disposed inside the N-type epitaxial layer; a P-type drain region is disposed in the buffer trap region; N-type source regions and a P-type body contact region are disposed in the P-type body region; an N-type base region and a P-type emitter region are disposed in the buffer trap region; gate and field oxide layers are disposed on the N-type epitaxial layer; polycrystalline silicon gates are disposed on the gate oxide layers; and a passivation layer and metal layers are disposed on the surface of the symmetrical transistor. P-type emitter region output and current density are improved without increasing the area of the transistor.

High-current N-type silicon-on-insulator lateral insulated-gate bipolar transistor

An isolation structure of a high-voltage driving circuit includes a P-type substrate and a P-type epitaxial layer; a high voltage area, a low voltage area and a high and low voltage junction terminal area are arranged on the P-type epitaxial layer; a first P-type junction isolation area is arranged between the high and low voltage junction terminal area and the low voltage area, and a high-voltage insulated gate field effect tube is arranged between the high voltage area and the low voltage area; two sides of the high-voltage insulated gate field effect tube and an isolation structure between the high-voltage insulated gate field effect tube and a high side area are formed as a second P-type junction isolation area.

Isolation structure of high-voltage driving circuit

A silicon on insulator N type semiconductor device, includes a N type drift region, a P type deep well, an N type buffer well, a P type drain region, an N type source region and a P type body contact region; a field oxide layer and a gate oxide layer arranged on a silicon surface, and a polysilicon lattice arranged on the gate oxide layer; and an N type triode drift region, a P type deep well, an N type triode buffer well, a P type emitting region, an N type base region, an N type source region and a P type body contact region; a field oxide layer and a gate oxide layer arranged on a silicon surface, and a polysilicon lattice arranged on the gate oxide layer.

Silicon on insulator integrated high-current N type combined semiconductor device

A switching power supply with a quick transient response is provided. A hysteretic control loop which comprises a hysteretic controller () and a control signal gate () is added to the original PWM control loop of the switching power supply. The hysteretic controller () is used to detect an output voltage (Vout) of the switching power supply and compare the output voltage (Vout) of the switching power supply with a reference voltage (Vref). When a load current (Iout) of the switching power supply is suddenly changed, the output voltage (Vout) of the switching power supply fluctuates. If the output voltage (Vout) of the switching power supply is in a setting range of the hysteretic voltage, output terminals (SELp, SELn) of the hysteretic controller () are in a low potential, and the control signal gate () selects output signals (Qp, Qn) from a PWM controller () as input signals of a gate signal drive circuit (). If the fluctuation of the output voltage (Vout) of the switching power supply exceeds the setting range of the hysteretic voltage, an output terminal (SELp, SELn) of the hysteretic controller () outputs a high potential, and the control signal gate () selects output signals (Qp, Qn) of the hysteretic controller () as input signals of the gate signal drive circuit (), so the operation of switching tubes () at the power lever () of the switching power supply is controlled to stabilize the output voltage (Vout).

Switching power supply with quick transient response

A switch level circuit () with dead time self-adapting control, which minimizes the switching loss in a switching power supply converter with synchronous rectification by changing a dead time between a high-side control transistor () and a low-side synchronous rectifying transistor (). The switch level circuit () includes the high-side control transistor () and the low-side synchronous rectifying transistor () which are controlled to be on and off by external control signals, and a waveform with a given duty cycle is outputted at a node (LX) between the two transistors. The switch level circuit () also includes a control module for adjusting the dead time. The control module comprises a sampling circuit () for detecting the current dead time at the node (LX), an adjusting circuit () for buffering and converting the sampling voltage sampled by the sampling circuit (), and a controlled delay unit () equipped with an external control input terminal, wherein the controlled delay unit () delays an external control signal and outputs the delayed signal to a controlled terminal of the low-side synchronous rectifying transistor () as a control signal. The switch level circuit () has simple structure, better performance and wide application range.

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Jiangsu, China

Shengli Lu