Koninklijke Philips Corporation N.V.

Philips Electronics North America Corporation

Optimum Semiconductor Technologies Inc.

Qualcomm Incorporated

Sandbridge Technologies, Inc.

Wuxi Dsp Technologies Inc.

Shenghong Wang

C John Glossner

Demetri J Giannopoulos

Mayan Moudgill

Ihor T Wacyk

Gary J Nacer

Arthur Joseph Hoane

Erdem Hokenek

Paul Gerard D'Arcy

Murugappan Senthilvelan

Vitaly Kalashnikov

Sabin Daniel Iancu

Arthur J Hoane

Muragappan Senthilvelan

Sabin D Iancu

A chaining bit decoder of a computer processor receives an instruction stream. The chaining bit decoder selects a group of instructions from the instruction stream. The chaining bit decoder extracts a designated bit from each instruction of the instruction stream to produce a sequence of chaining bits. The chaining bit decoder decodes the sequence of chaining bits. The chaining bit decoder identifies zero or more instruction stream dependencies among the selected group of instructions in view of the decoded sequence of chaining bits. The chaining bit decoder outputs control signals to cause one or more pipelines stages of the processor to execute the selected group of instructions in view of the identified zero or more instruction stream dependencies among the group sequence of instructions.

Method and apparatus for enabling a processor to generate pipeline control signals

A computing device determines that a current software thread of a plurality of software threads having an issuing sequence does not have a first instruction waiting to be issued to a hardware thread during a clock cycle. The computing device identifies one or more alternative software threads in the issuing sequence having instructions waiting to be issued. The computing device selects, during the clock cycle by the computing device, a second instruction from a second software thread among the one or more alternative software threads in view of determining that the second instruction has no dependencies with any other instructions among the instructions waiting to be issued. Dependencies are identified by the computing device in view of the values of a chaining bit extracted from each of the instructions waiting to be issued. The computing device issues the second instruction to the hardware thread.

Opportunity multithreading in a multithreaded processor with instruction chaining capability

Disclosed are an opportunistic multi-thread method and processor, the method comprising the following steps: if a zeroth thread, a first thread, a second thread and a third thread all have instructions ready to be executed, then a zeroth clock period, a first clock period, a second clock period and a third clock period are respectively allocated to the zeroth thread, the first thread, the second thread and the third thread; if one of the threads cannot issue an instruction within a specified clock period because the instruction is not ready, and the previous thread still has an instruction ready to be executed after issuing certain instructions in the previous specified clock period, then the previous thread will take the specified clock period. The processor comprises an instruction cache, an instruction decoder, an instruction pipeline controller and an arithmetic logic unit; the opportunistic multi-thread processor adds for each stage of production line a prediction circuit for an effective thread instruction and a set of two-dimensional thread identity registers.

Opportunistic multi-thread method and processor

A processing device identifies a set of software threads having instructions waiting to issue. For each software thread in the set of the software threads, the processing device binds the software thread to an available hardware context in a set of hardware contexts and stores an identifier of the available hardware context bound to the software thread to a next available entry in an ordered list. The processing device reads an identifier stored in an entry of the ordered list. Responsive to an instruction associated with the identifier having no dependencies with any other instructions among the instructions waiting to issue, the processing device issues the instruction waiting to issue to the hardware context associated with the identifier.

Multithreading using an ordered list of hardware contexts

A method is described for operation of a DMA engine. Copying is initiated for transfer of a first number of bytes from first source memory locations to first destination memory locations. Then, a halt instruction is issued before the first number of bytes are copied. After copying is stopped, a second number of bytes is established, encompassing those bytes remaining to be copied. After the transfer is halted, a quantity of the second number of bytes is identified. Quantity information is then generated and stored. Second source memory locations are identified to indicate where the second number of bytes are stored. Second source memory location information is then generated and stored. Second destination memory locations are then identified to indicate where the second number of bytes are to be transferred. Second destination memory location information is then generated and stored.

Haltable and restartable DMA engine

A circuit is described including a clock input for at least one clock signal. Only one clock buffer is connected to the clock input to generate, based on the at least one clock signal, at least a first modified clock signal and a second modified clock signal. A plurality of flip-flops are connected to the clock buffer. Each of the flip-flops receive the first and second modified clock signals. A plurality of data inputs are each connected to at least one of the plurality of flip-flops to provide input data to the plurality of flip-flops. A plurality of data outputs each are connected to at least one of the plurality of flip-flops to provide output data from the plurality of flip-flops. Each of the plurality of flip-flops transform the input data to the output data utilizing the first modified clock signal and the second modified clock signal.

Power saving circuit using a clock buffer and multiple flip-flops

A cache memory for use in a multithreaded processor includes a number of set-associative thread caches, with one or more of the thread caches each implementing a thread-based eviction process that reduces the amount of replacement policy storage required in the cache memory. At least a given one of the thread caches in an illustrative embodiment includes a memory array having multiple sets of memory locations, and a directory for storing tags each corresponding to at least a portion of a particular address of one of the memory locations. The directory has multiple entries each storing multiple ones of the tags, such that if there are n sets of memory locations in the memory array, there are n tags associated with each directory entry. The directory is utilized in implementing a set-associative address mapping between access requests and memory locations of the memory array. An entry in a particular one of the memory locations is selected for eviction from the given thread cache in conjunction with a cache miss event, based at least in part on at least a portion of a thread identifier of the given thread cache.

Method and apparatus for multithreaded cache with cache eviction based on thread identifier

A cache memory for use in a multithreaded processor includes a number of set-associative thread caches, with one or more of the thread caches each implementing an eviction process based on access request address that reduces the amount of replacement policy storage required in the cache memory. At least a given one of the thread caches in an illustrative embodiment includes a memory array having multiple sets of memory locations, and a directory for storing tags each corresponding to at least a portion of a particular address of one of the memory locations. The directory has multiple entries each storing multiple ones of the tags, such that if there are n sets of memory locations in the memory array, there are n tags associated with each directory entry. The directory is utilized in implementing a set-associative address mapping between access requests and memory locations of the memory array. An entry in a particular one of the memory locations is selected for eviction from the given thread cache in conjunction with a cache miss event, based at least in part on at least a portion of an address in an access request associated with the cache miss event.

Method and apparatus for multithreaded cache with simplified implementation of cache replacement policy

An improved technique of interfacing a computer lighting device to a control computer is disclosed, wherein a hardware device is interposed between the control computer and the lighting device. The hardware device handles certain functions in hardware, thereby permitting the microprocessor at the lighting device to incur substantially less processing load.

Communication port control module for lighting systems

A method and apparatus for voltage/current overage condition protection for a lighting control circuit. The method provides a hybrid software and hardware solution to take advantage of the useful attributes of both. Overages are sensed in hardware by digital comparators, where the thresholds used as the basis for comparison are predefined in software. When an overage is detected, the circuit outputs, which are controlled by a plurality of counters, are changed by changing the source of the pulse width data used by the counters from software control to predetermined minima stored in a plurality of registers.

Method and apparatus for providing overload protection for a circuit

An enhanced protocol for enabling manual control of electronic ballasts in lighting control networks which are compliant with the DALI standard, as well as a communications interface apparatus for such a ballast for decoding both the standard DALI messages, as well as the manual control messages available in the enhanced protocol of the present invention are presented.

Protocol enhancement for lighting control networks and communications interface for same

A method and apparatus for providing closed loop feedback control is presented. The method consists of a hybrid software and hardware solution to take advantage of the useful attributes of both. Analog signals output by the device are sampled at a rate sufficient to preserve all necessary high frequency information, and preprocessed at high speed in hardware. The outputs of the preprocessing stage are then operated on in software at much lower speeds. The method and apparatus allow for the complex real time processing of feedback signals in the digital domain, yet allow the cost efficiencies and programming flexibility of a standard micro-controller to be utilized.

Universal hardware/software feedback control for high-frequency signals

A digital lamp signal processor senses lamp current and lamp voltage in real time. These two signals are sufficient to obtain information, such as real lamp power calculation, necessary to control ballast operation and fault detection. The apparatus measures the phase of lamp current and voltage, the peak current and voltage, and calculates the average lamp current and voltage. The digital lamp signal processor eliminates the effect of parasitic capacitance of power wiring and a signal condition circuit. It may detect and control hard switching and apply over current and voltage protection. The apparatus directly processes AC signals, allowing for simple and easily integrated single chip design.

Digital lamp signal processor

An apparatus for power factor control includes a capacitor for producing a substantially DC voltage and a switch for controlling the amount of energy stored in the capacitor in response to a switching signal. The switching signal is produced by the power factor controller and is based on a sinusoidal waveform that is independent of the waveform of an AC supply voltage for energizing an electric load.

Apparatus for power factor control

A ballast for operating different types of lamp loads through identification of the lamp type during steady state operation of the lamp load. Lamp type recognition is achieved based on a comparison of the lamp load voltage and lamp load current data points stored in a random-access memory of a microprocessor to a plurality of V-I characteristic curves stored in a read-only memory of the microprocessor. Through this comparison, the ballast can distinguish among a number of different lamp loads having the same starting voltage.

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Yorktown Heights, NY, United States of America

Shenghong Wang