No. 24 Research Institute of China Electronics Technology Group Corporation

Chongqing University

Chongqing Gigachip Technology Co. Ltd.

Shengdong Hu

Jun Luo

Dongbing Fu

Jian'an Wang

Yuxin Wang

Daiguo Xu

Tao Liu

Yan Wang

Minming Deng

Guangbing Chen

Ruzhang Li

Zhengping Zhang

Lu Liu

Xu Wang

Zhou Yu

Zicheng Xu

Fang Tang

Xichuan Zhou

Zhi Lin

Qi Yuan

Shu Han

Jianlin Zhou

A multi-bit resolution sub-pipeline structure for measuring a jump magnitude of a transmission curve, comprising: a sub-analog-to-digital converter having n-bit resolution configured to quantize input analog voltage signals and output digital voltage signals; a sub-digital-to-analog converter having n-bit resolution configured to convert the digital voltage signals output by the sub-analog-to-digital converter into corresponding analog voltage signals; a decoder having n-bit resolution configured to decode an n-bit binary input signal; and a switched-capacitor amplification unit configured to, when in a normal mode, perform sampling and residue amplification on the input analog voltage signals; and when in a test mode, measure the jump magnitude of the transmission curve corresponding to each decision level. Magnitude measurement of a transmission curve is performed within 2clock periods, th and a measurement result is sent to a back-end digital domain of the A/D converter for correction.

Multi-bit resolution sub-pipeline structure for measuring jump magnitude of transmission curve

The present disclosure provides a low-jitter frequency division clock circuit, including: a clock control signal generation circuit, to generate clock signals having different phases; a low-level narrow pulse width clock control signal generation circuit, to generate a low-level narrow pulse width clock control signal; a high-level narrow pulse width clock control signal generation circuit, to generate a high-level narrow pulse width clock control signal; and a frequency division clock generation circuit, to generate a frequency division clock signal according to low-level narrow pulse width clock control signal and high-level narrow pulse width clock control signal. The delay from a clock input end to an output end of low-jitter frequency division clock circuit is up to three logic gates. Compared with traditional divide-by-2 frequency division clock circuits based on D-flip-flop, the low-jitter frequency division clock circuit of the present disclosure has fewer logic gates, a shorter delay, and lower jitter.

Low-jitter frequency division clock clock circuit

The present disclosure relates to a high-speed superjunction lateral insulated gate bipolar transistor, and belongs to the technical field of semiconductor power devices. Fast turn-off can be achieved by replacing the lightly doped substrate of the existing bulk silicon superjunction lateral insulated gate bipolar transistor with heavily doped substrate, breakdown voltage of the device is ensured by reasonably setting the total number of impurities in each drift region of the over junction-sustaining voltage layer, and further application thereof in integrated circuits is realized by providing the semiconductor second substrate region and the semiconductor isolation region. A high speed superjunction laterally insulated gate bipolar transistor according to the present disclosure solves the contradiction between cost of the superjunction laterally insulated gate bipolar transistor and achievement of fast turn-off on a bulk silicon substrate.

High-speed superjunction lateral insulated gate bipolar transistor

Growing community of inventors

Chongqing, China

Shengdong Hu