Huawei Technologies Co., Limited

Shengbing Yang

Wenhua Sun

Xiaobo Wang

Wenguang Xu

Jihui Wang

Bingbo Li

Youhao Deng

A method and system for processing correction field information are provided. The method includes: receiving a packet, and obtaining a first correction value carried by the packet; obtaining first time information and second time information; obtaining a second correction value according to the first correction value and the first time information; setting the second correction value in the packet; setting the second time information in the packet; obtaining third time information and fourth time information; obtaining a third correction value according to the second correction value, the second time information, the third time information, and the fourth time information; and setting the third correction value in the packet. The processing of the time information and the processing of the correction field information are performed with a set of processing mechanism, and the implementation is simpler.

Method and system for processing correction field information

A method and device for improving clock stability are provided. The method includes: determining whether a difference between a current sender timestamp (ST) and a current receiver timestamp (RT) is a mutated value; pre-processing the ST and RT, if the difference between the ST and RT is a mutated value; acquiring a service clock according to the pre-processed ST and RT; and sending time division multiplex (TDM) data according to the service clock. Through the embodiments of the present disclosure, a packet delay variance (PDV) may be smoothed, the impairment of the PDV on clock recovery may be reduced, the quality of the clock recovery may be improved, and the problem of clock synchronization may be solved through the mutation processing on the timestamps.

Method and device for improving clock stability

A precise-clock synchronization method and system and a precise-clock frequency/time synchronization device are provided. In the embodiments of the present invention, two time stamp engines are provided at a slave clock side. A relative time stamp engine provides a relative arrival time stamp. An absolute time stamp engine provides an absolute arrival time stamp. The frequency/time synchronization is calculated by using different time stamps obtained from different time stamp engines, so the frequency synchronization and time synchronization of the master clock and the slave clock may be separately accomplished, and one synchronization function may be enabled or disabled. Therefore, the frequency synchronization and time synchronization of the master clock and the slave clock do not interfere with each other, thus greatly reducing the occupied link bandwidth resources.

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Shenzhen, China

Shengbing Yang