Shanghai Hua Hong Nec Electronics Company, Limited

Shanghai Hua Hong Electronics Co., Ltd.

Shengan Xiao

Fei Wang

Feng Han

Wensheng Qian

Jiquan Liu

Wei Ji

Xiaohua Cheng

Yanping Liu

A semiconductor device includes: a P+ substrate; a P&#x2212; epitaxial layer over the P+ substrate; a P-well and an N&#x2212; drift region in the P&#x2212; epitaxial layer and laterally adjacent to each other; an N+ source region in the P-well and connected to a front-side metal via a first contact electrode; an N+ drain region in the N&#x2212; drift region and connected to the front-side metal via a second contact electrode; a gate structure on the P&#x2212; epitaxial layer and connected to the front-side metal via a third contact electrode; and a metal plug through the P&#x2212; epitaxial layer and having one end in contact with the P+ substrate and the other end connected to the front-side metal, the metal plug being adjacent to one side of the N+ source region that is farther from the N&#x2212; drift region. A method for fabricating the semiconductor device is also disclosed.

Semiconductor device and method for fabricating the same

A super-junction device including a unit region is disclosed. The unit region includes a heavily doped substrate; a first epitaxial layer over the heavily doped substrate; a second epitaxial layer over the first epitaxial layer; a plurality of first trenches in the second epitaxial layer; an oxide film in each of the plurality of first trenches; and a pair of first films on both sides of each of the plurality of first trenches, thereby forming a sandwich structure between every two adjacent ones of the plurality of first trenches, the sandwich structure including two first films and a second film sandwiched therebetween, the second film being formed of a portion of the second epitaxial layer between the two first films of a sandwich structure. A method of forming a super-junction device is also disclosed.

Super-junction device and method of forming the same

A superjunction structure with unevenly doped P-type pillars () and N-type pillars () is disclosed. The N-type pillars () have uneven impurity concentrations in the vertical direction and the P-type pillars () have two or more impurity concentrations distributed both in the vertical and lateral directions to ensure that the total quantity of P-type impurities in the P-type pillars () close to the substrate () is less than that of N-type impurities in the N-type pillars close to the substrate; the total quantity of P-type impurities in the P-type pillars close to the top of the device is greater than that of N-type impurities in the N-type pillars close to the top. A superjunction MOS transistor and manufacturing method of the same are also disclosed. The superjunction structure can improve the capability of sustaining current-surge of a device without affecting or may even reduce the on-resistance of the device.

Superjunction structure, superjunction MOS transistor and manufacturing method thereof

A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate, forming an epitaxial layer on a top surface of the semiconductor substrate and having a predetermined thickness, and forming a plurality of trenches in the epitaxial layer. The trenches are formed in the epitaxial layer and have a predetermined depth, top width, and bottom width. Further, the method includes performing a first trench filling process to form a semiconductor layer inside of the trenches using a mixture gas containing at least silicon source gas and halogenoid gas, stopping the first trench filling process when at least one trench is not completely filled, and performing a second trench filling process, different from the first trench filling process, to fill the plurality of trenches completely.

Semiconductor structures and fabrication methods including trench filling

A method for manufacturing trench type super junction device is disclosed. The method includes the step of forming one or more P type implantation regions in the N type epitaxial layer below the bottom of each trench. By using this method, a super junction device having alternating P type and N type regions is produced, wherein the P type region is formed by P type silicon filled in the trench and P type implantation regions below the trench. The present invention can greatly improve the breakdown voltage of a super junction MOSFET.

Method for manufacturing trench type superjunction device and trench type superjunction device

A superjunction device is disclosed, wherein P-type regions in an active region are not in contact with the N+ substrate, and the distance between the surface of the N+ substrate and the bottom of the P-type regions in the active region is greater than the thickness of a transition region in the N-type epitaxial layer. Methods for manufacturing the superjunction device are also disclosed. The present invention is capable of improving the uniformity of reverse breakdown voltage and overshoot current handling capability in a superjunction device.

Superjunction device and method for manufacturing the same

A terminal structure for superjunction device is disclosed. The terminal structure comprises from inside out at least one P type implantation ring and several P type trench rings formed in an N type epitaxial layer to form alternating P type and N type regions. A channel cut-off ring is formed at the border of the device. The P type implantation ring is formed adjacent to the active area of the device and covers at least one trench ring. A terminal dielectric layer is formed to cover the P type implantation ring and the trench rings. A plurality of field plates are formed above the terminal dielectric layer. Methods of manufacturing terminal structure are also disclosed.

Terminal structure for superjunction device and method of manufacturing the same

A method of etching and tilling deep trenches is disclosed, which includes: forming an ONO(oxide-nitride-oxide) sandwich layer on a semiconductor substrate; forming deep trenches by using top oxide of the sandwich layer as a stop layer; removing the top oxide and middle SiN of the sandwich layer; tilling the deep trenches with epitaxial film or polysilicon film; polishing the wafer to get a planarized surface by stopping at the surface of the bottom oxide layer; removing the bottom oxide layer.

Method for etching and filling deep trenches

The invention is related to a semiconductor device with alternately arranged P-type and N-type thin semiconductor layers and method for manufacturing the same. For P-type device, the method includes trench formation, thermal oxide formation on trench sidewalls, N-type silicon formation in trenches, N-type impurity diffusion through thermal oxide into P-type epitaxial layer, oxidation of N-type silicon in trenches and oxide removal. In the semiconductor device, N-type thin semiconductor layers are formed by N-type impurity diffusion through oxide to P-type epitaxial layers, and trenches are filled with oxide. With this method, relatively low concentration impurity in high voltage device can be realized by current mass production process, and the device development cost and manufacturing cost are decreased.

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Shanghai, China

Shengan Xiao