Xilinx, Inc.

Sheng Zhou

Ralph D Wittig

Philip Bryn James-Roxby

Sonal Santan

Henry E Styles

Fernando J Martinez Vallina

Jeffrey M Fifield

Devadas Varma

Dong Li

Qin Qiong Zhang

Stephen Andrew Neuendorffer

Pradip Jha

Alec J Wong

Bin Ochotta

Charles Kwok-Wah Lo

Charles Kwah-Wah Lo

Kwok-Wah Lo

High level synthesis can include detecting, using a processor, an enumerated operation within an instruction of a loop construct of an application, determining, using the processor, whether the loop construct meets a modification condition, and responsive to determining that the loop construct meets the modification condition, modifying, using the processor, the loop construct to calculate the enumerated operation as a compile time constant, wherein the modified loop construct is functionally equivalent to the loop construct.

Operation processing for high level synthesis

High level synthesis for a circuit design may include detecting, using a processor, an encrypted, high level programming language (HLL) core for inclusion in a circuit design, decrypting, using the processor, the encrypted HLL core into volatile memory, and generating, using the processor, an encrypted, intermediate representation (IR) of the circuit design including an encrypted IR of the HLL core. An encrypted hardware description language (HDL) circuit design may be generated, using the processor, from the encrypted IR of the circuit design. The encrypted HDL circuit design includes an encrypted HDL core that is functionally equivalent to the encrypted HLL core.

High level programming language core protection for high level synthesis

An integrated circuit (IC) includes a first region being static and providing an interface between the IC and a host processor. The first region includes a first interconnect circuit block having a first master interface and a second interconnect circuit block having a first slave interface. The IC includes a second region coupled to the first region. The second region implements a kernel of a heterogeneous, multiprocessor design and includes a slave interface coupled to the first master interface of the first interconnect circuit block and configured to receive commands from the host processor. The second region also includes a master interface coupled the first slave interface of the second interconnect circuit block, wherein the master interface of the second region is a master for a memory controller.

Heterogeneous multiprocessor platform targeting programmable integrated circuits

OpenCL program compilation may include generating, using a processor, a register transfer level (RTL) description of a first kernel of a heterogeneous, multiprocessor design and integrating the RTL description of the first kernel with a base platform circuit design. The base platform circuit design provides a static interface within a programmable integrated circuit to a host of the heterogeneous, multiprocessor design. A first configuration bitstream may be generated from the RTL description of the first kernel using the processor. The first configuration bitstream specifies a hardware implementation of the first kernel and supporting data for the configuration bitstream. The first configuration bitstream and the supporting data may be included within a binary container.

Heterogeneous multiprocessor program compilation targeting programmable integrated circuits

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San Jose, CA, United States of America

Sheng Zhou