Maxlinear, Inc.

University of California

Sheng Ye

Curtis Ling

Xuefeng Chen

Anand Anandakumar

Glenn Chang

Raymond Montemayor

Kishore Seendripu

Eric Fogleman

Kok Lim Chan

Timothy Leo Gallagher

Mingrui Zhu

Pawandeep Taluja

Sridhar Ramesh

James Xiaohui Qiu

Raja Pullela

Vamsi Paidi

Morten Damgaard

Stephane Laurent-Michel

Seung-Chul Hong

Subramanian Anantharaman Chandrasekarapuram

Sangeetha Gopalakrishnan

Amir Hadji-Abdolhamid

Tienyu Chang

Ian Galton

Paul P Chominski

Raghava Manas Bachu

Anand K Anandkumar

Anand Anandakumer

Methods and systems for providing reduced bandwidth acquisition latency may comprise communicating a reservation request for bandwidth allocation for devices operating under a wired network protocol, where the reservation request may be sent by wired network devices via a wireless network protocol over a wireless network. Bandwidth may be allocated in the wired network for the requesting devices by a network controller. Data may be communicated with the requesting devices via the wired network. The wired network communication protocol may comprise a multimedia over cable alliance (MoCA) standard. The wireless protocol may comprise an IEEE 802.11x standard, a Bluetooth standard, and/or any non-public network protocol. The communication of the reservation request via the wireless protocol may decrease a latency of the wired network. A medium access plan (MAP) may be generated by the network controller based on the reservation request and may comprise a bandwidth allocation for the requesting devices.

Channel-sensitive power control

Systems and methods are provided for low-power asynchronous data links. A receiver may obtain from signals, received from a transmitter over low-power asynchronous links, recovery information embedded into the signals at the transmitter, and may determine based on the recovery information, control parameters that may be used in configuring a control signal applied during processing of the signals. The signals may be processed based on the control signal, with the processing comprising extraction of data embedded in the signals at the transmitter. The transmitter may generate, based on an input datastream, signals configured for transmission to the receiver, over low-power asynchronous data links, and may embed into the signals, the recovery information that enables determining, at the receiver, parameters relating to the signals and/or to the generating of the signals. The control parameters may comprise parameters relating to the signals and/or processing of the signals at the transmitter.

Low-power asynchronous data links

Methods and systems for a baseband cross-bar may comprise receiving one or more radio frequency (RF) signals in a wireless communication device via antennas coupled to a plurality of receiver paths in the wireless device. The received RF signals may be converted to baseband frequencies. One or more of the down-converted signals may be coupled to receiver paths utilizing a baseband cross-bar. The baseband cross-bar may comprise a plurality of switches, which may comprise CMOS transistors. In-phase and quadrature signals may be processed in the one or more of the plurality of receiver paths. The one or more RF signals comprise cellular signals and/or global navigation satellite signals. A single-ended received RF signal may be converted to a differential signal in one or more of the plurality of receiver paths. The baseband cross-bar may be controlled utilizing a reduced instruction set computing (RISC) processor.

Method and system for a baseband cross-bar

Methods and systems for a sampled loop filter in a phase locked loop (PLL) may comprise a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider. The PLL generates at least one clock signal, and the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero. The frequency divider may be a fractional-N divider. A second switch in said sampled loop filter may have switching times that are non-overlapping with switching times of the at least one switch. Capacitors may be coupled to ground from each terminal of the second switch.

Method and system for a sampled loop filter in a phase locked loop (PLL)

Systems and methods are provided for handling jitter improvement in transmitters. During processing of input data for serial transmission, it may be determined if jitter may occur, and when jitter occurs one or more adjustments may be determined, based on dummy data, to reduce jitter in an output corresponding to the input data. The one or more adjustments may then be applied during processing of the input data, to reduce jitter in a serial output corresponding to the input data. The dummy data may be generated based on the input data. The dummy data may be configured such that it may generate corresponding dummy current pulses which may be used in controlling supply variations during generation of the serial output. The use of the dummy data may be selectively turned on or off.

Jitter improvement in serializer-deserializer (SerDes) transmitters

Methods and systems for multi-path video and network channels may comprise a communication device comprising a wideband tuner (WB) and a narrowband tuner (NB). A video channel and a network channel may be received in the WB when the device is operating in a first stage. A video channel and a network channel may be received in the WB and the network channel may also be received in the NB when the device is operating in a second stage. The network channel may be received in the NB when the device is operating in a third stage. The reception of the network channel from both the WB and NB may enable a continuous reception of the network channel in a transition between the first and third stages. The WB may be operable to receive a plurality of channels and the NB may be operable to receive a single channel.

Method and system for multi-path video and network channels

Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

Method and system for time interleaved analog-to-digital converter timing mismatch estimation and compensation

A phase locked loop may be operable to generate, utilizing a frequency multiplier, a reference clock signal whose frequency is an integer M times a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. The phase locked loop may enable usage of both rising and falling edges of the crystal clock signal, based on the reference clock signal. The phase locked loop may perform an operation of the phase locked loop based on the enabling. The phase locked loop may perform a phase comparison function, based on both rising and falling edges of the crystal clock signal. By utilizing a sampled loop filter in the phase locked loop, the phase locked loop may eliminate, at an output of a charge pump in the phase locked loop, disturbance which is associated with duty cycle errors of the crystal clock signal.

Reference-frequency-insensitive phase locked loop

An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

Method and system for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCS)

A transceiver comprises local oscillator circuitry, phase noise determination circuitry, mixing circuitry, and digital signal processing circuitry. The local oscillator circuitry is operable to generate a local oscillator signal. The phase noise determination circuitry is operable to introduce a frequency-dependent phase shift to the local oscillator signal to generate a phase-shifted version of the local oscillator signal. The mixing circuitry is operable to mix the local oscillator signal and the phase-shifted version of the local oscillator to generate a baseband signal having an amplitude proportional to a phase difference between the local oscillator signal and the phase-shifted version of the local oscillator signal. The digital signal processing circuitry is operable to process the baseband signal to determine a phase error of the local oscillator signal, and perform signal compensation based on the determined phase error.

Phase noise suppression

A system comprises a microwave backhaul outdoor unit having a first resonant circuit, phase error determination circuitry, and phase error compensation circuitry. The first resonant circuit is operable to generate a first signal characterized by a first amount of phase noise and a first amount of temperature stability. The phase error determination circuitry is operable to generate a phase error signal indicative of phase error between the first signal and a second signal, wherein the second signal is characterized by a second amount of phase noise that is greater than the first amount of phase noise, and the second signal is characterized by a second amount of temperature instability that is less than the first amount of temperature instability. The phase error compensation circuitry is operable to adjust the phase of a data signal based on the phase error signal, the adjustment resulting in a phase compensated signal.

Outdoor unit resonator correction

A method and system for duty-cycled high speed clock and data recovery with forward error correction are provided. The system operates on a first digital signal comprising a first plurality of samples and a second digital signal comprising a second plurality of samples. The second plurality of samples may be a subset of the first plurality of samples, for example, if the first and second pluralities of samples are generated by one analog-to-digital converter. A clock and data recovery module is operable to produce a timing indication according the second digital signal. The second plurality of samples is sampled intermittently. The discontinuity between bursts of samples in the second signal corresponds to a duty cycle. A forward error correction module is operable to produce a digital error-corrected signal according to the first digital signal and the timing indication.

Duty-cycled high speed clock and data recovery with forward error correction assist

Each of a plurality of modules comprises a respective one of a plurality of antenna elements, and each of a subset of the plurality of modules comprising a respective one of a plurality of transceivers, wherein the plurality of modules are interconnected via one or more communication links. The circuitry may be operable to receive a calibration signal via the plurality of antenna elements, determine, for each one of the antenna elements, a time and/or phase of arrival of the calibration signal, calculate, based on the time and/or phase of arrival of the calibration signal at each of the plurality of antenna elements, electrical distances between the plurality of antenna elements on the one or more communication links, and calculate beamforming coefficients for use with the plurality of antenna elements based on the electrical distances.

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Carlsbad, CA, United States of America

Sheng Ye