Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Sheng-Wen Huang

Chung-Pin Chou

Jun-Xiu Liu

Chi-Ming Tsai

Jun Xiu Liu

Kai-Lin Chuang

Chih-Chung Huang

Yan-Cheng Chen

Hsin-Lun Tseng

Wei-Lin Chu

Ming-Chang Lee

In-Tsang Lin

Chun-Wei Liao

Tien-Wen Wang

Hsin-Hui Chou

Yu-Ting Wang

Jui-Kuo Lai

Yao-Tsu Yang

Some implementations described herein provide techniques and apparatuses for a semiconductor processing tool including an electrostatic chuck having a voltage-regulation system to regulate an electrical potential throughout regions of a semiconductor substrate positioned above the electrostatic chuck. The voltage-regulation system may determine that an electrical potential within a region of the semiconductor substrate does not satisfy a threshold. The voltage-regulation system may, based on determining that the electrical potential throughout the region does not satisfy the threshold, position one or more electrically-conductive pins within the region. While positioned within the region, the one or more electrically-conductive pins may change the electrical potential of the region.

Semiconductor processing tool and methods of operation

This disclosure is directed to solutions of detecting and classifying wafer defects using machine learning techniques. The solutions take only one coarse resolution digital microscope image of a target wafer, and use machine learning techniques to process the coarse SEM image to review and classify a defect on the target wafer. Because only one coarse SEM image of the wafer is needed, the defect review and classification throughput and efficiency are improved. Further, the techniques are not distractive and may be integrated with other defect detecting and classification techniques.

Machine learning on wafer defect review

A method includes providing a first design layout including cells; updating a first cell in the plurality of cells using optical proximity correction to provide a first updated cell and a data set; training a model based on a layout-dependent parameter of a second design layout; and updating a second cell based on the data set and the model to provide a second updated cell. The model includes an input layer, a hidden layer and an output layer. Training the model includes obtaining converged values of nodes of the hidden layer. Obtaining converged values of nodes of the hidden layer includes providing information on edge segments before and after lithography enhancement to the input layer and the output layer, respectively, until values of nodes of the hidden layer attains convergence in terms of a cost function.

Method and system for layout enhancement based on inter-cell correlation

A method and a system of performing layout enhancement include: providing a first design layout comprising a plurality of cells; updating a first cell in the plurality of cells using optical proximity correction to provide a first updated cell and a data set; updating a second cell from remaining cells in the first design layout based on the data set to provide a second updated cell; and manufacturing a mask based on the first updated cell and the second updated cell in the first design layout.

A system includes an inspection device and an image processing unit. The inspection device is configured to scan a wafer to generate an inspected image. The image processing unit is configured to receive the inspected image, and is configured to analyze the inspected image by using at least one deep learning algorithm in order to determine whether there is any defect image shown in a region of interest in the inspected image. When there is at least one defect image shown in the region of interest in the inspected image, the inspection device is further configured to magnify the region of interest in the inspected image to generate a magnified inspected image for identification of defects.

Inspection and cleaning system and method for the same

The present invention relates to a 3-D waveguide coupling device capable of two-step coupling and a manufacture method thereof, the 3-D waveguide coupling device comprises: a first substrate, at least one waveguide layer, at least one assisting grating, at least one coupling material layer, and at least one 3-D tapered structure layer, wherein 3-D waveguide coupling device is able to couple the light into the waveguide layer by way of two-step coupling through the 3-D tapered structure layer, the coupling material layer and the assisting grating. Moreover, the light can also be coupled out from the waveguide layer through the assisting grating, the coupling layer, and the 3-D tapered structure. The manufacture method is adapted to fabricate the 3-D waveguide coupling device capable of two-step coupling via the present semiconductor process technology without increasing any other new equipment.

3-D waveguide coupling device capable of two-step coupling and manufacture method thereof

Growing community of inventors

Hsinchu, Taiwan

Sheng-Wen Huang