Taiwan Semiconductor Manufacturing Comp. Ltd.

Phison Electronics Corporation

Cytoaurora Biotechnologies, Inc.

Au Optronics Corporation

Azurewave Technologies, Inc.

Sheng-Wen Chen

Chung-Er Huang

Hsin-Cheng Ho

Yu-Ting Lin

Shih-Yang Sun

Szu-An Wu

Wei-Yung Chen

Ming Chen

Zhen-Hong Hung

Shiu-Ko JangJian

Ying-Lang Wang

Ting-Chun Wang

Che-Hao Chang

Lun-Kuang Tan

Wei-Ming You

Chih-Ming Chen

Jen-Chu Wu

Shiu-Ko Jangjian

Chia Ping Lo

Yan-Hua Lin

Hei-Jen Jou

Shih Yu-Shen

Wen-Kuei Liu

Yu-Ku Lin

Hung Jui Chang

Chin Kun Lan

Chin-Te Huang

Jeng-Yang Pan

Hung-Jui Chang

Ching-Jui Hsiao

Chun-Wei Chang

Po-Min Cheng

Wei-Ting Wei

Bo-Jing Lin

Yu-Min Hung

Tsai-Fen Lee

Yen-Po Lin

Chen-Yi Huang

Ching-Chung Cheng

Chung-Kuang Chen

Po-Jung Chou

Shin-Yang Sun

Yung-Hsiang Tsao

Guang-Ci Ye

A contactless selection device, a light sensing structure thereof, and a biological particle selection apparatus are provided. The light sensing structure includes a substrate, an insulating layer, an electrode layer, and a photoelectric layer, the latter two of which are respectively formed on two opposite sides of the substrate. The photoelectric layer includes a plurality of collector regions, a plurality of base regions respectively formed in the collector regions, and a plurality of emitter regions that are respectively formed in the base regions. Each of the emitter regions includes a plurality of emitter pads formed in the corresponding base region. Each of the base regions, the corresponding collector region, and the corresponding emitter region are jointly formed as a vertical transistor. The insulating layer covers and separates the vertical transistors and an end of each of the emitter pads is exposed from the insulating layer.

Contactless selection device, light sensing structure thereof, and biological particle selection apparatus

A contactless selection device, a light triggering structure thereof, and a biological particle selection apparatus are provided. The light triggering structure includes a first substrate, a first electrode layer formed on the first substrate, a photodiode layer formed on the first electrode layer, and an insulating layer that covers the photodiode layer. The photodiode layer has a thickness within a range from 1 μm to 3 μm, and includes a first doped layer, an I-type layer, and a second doped layer, which are sequentially stacked from the first electrode layer. The second doped layer includes a plurality of triggering pads spaced apart from each other. Each of the triggering pads has a width within a range from 3 μm to 7 μm, and a distance between any two of the triggering pads adjacent to each other is less than or equal to 2 μm.

Contactless selection device, light triggering structure thereof, and biological particle selection apparatus

A signal re-driving device, a data storage system and a mode control method are provided. The method includes the following steps. A first signal is received via a receiving circuit of the signal re-driving device. An analog signal feature is detected the receiving circuit. A first mode is entered according to the analog signal feature. The first signal is modulated and a second signal is outputted in the first mode. The second signal is sent via a sending circuit of the signal re-driving device. A digital signal feature is detected via the receiving circuit. And, the first mode is switched to a second mode according to the digital signal feature.

Signal re-driving device, data storage system and mode control method

A quasi-soft catcher, a quasi-soft capture device, and a method for using the same are provided. The quasi-soft catcher includes a base and a plurality of protruding structures for capturing at least one target biological particle from a specimen. The protruding structures are regularly arranged on a board surface of the base. Each of the protruding structures includes an outer portion configured to touch the at least one target biological particle and an inner portion that is connected between the board surface and the outer portion, and a structural strength of the inner portion is less than that of the outer portion. The board surface has an interspace region arranged outside of the protruding portions, and the interspace region occupies 20-80% of the board surface.

Quasi-soft catcher, quasi-soft capture device, and method using the same

Microfluidic chip

A retiming circuit module, a signal transmission system and a signal transmission method are disclosed. The retiming circuit module includes a path control circuit and a multipath signal transmission circuit. The multipath signal transmission circuit includes a plurality of parallel signal transmission paths. The path control circuit is configured to control the multipath signal transmission circuit to perform signal transmission between an upstream device and a downstream device based on a first parallel signal transmission path in the parallel signal transmission paths during a period of a handshake operation performed between the upstream device and the downstream device. The path control circuit is further configured to control the multipath signal transmission circuit to perform the signal transmission based on a second parallel signal transmission path in the parallel signal transmission paths after the handshake operation is finished.

Retiming circuit module, signal transmission system and signal transmission method

A microfluidic device includes a lower casing and an upper casing covering the lower casing. The lower casing includes a lower base wall having a top surface and a plurality of spaced-apart columns that protrude upwards from the top surface. The upper casing includes an upper base wall. A first gap between the upper base wall and a column top surface of each of the columns is large enough to permit passage of large biological particles of a liquid sample, and a second gap between any two adjacent ones of the columns is not large enough to permit passage of the large biological particles and is large enough to permit passage of small biological particles of the liquid sample.

Microfluidic device

A catcher, a capture device, and a method for capturing at least one target biological particle are provided. The catcher includes a base and a plurality of capture arms extending from the base and spaced apart from each other. Each of the capture arms has a free end portion configured to capture a target biological particle and a supporting segment connected between the free end portion and the base. The supporting segment of each of the capture arms is arranged in a projection space defined by orthogonally projecting the free end portion along a height direction onto the base. When the target biological particle is captured by two of the capture arms that are bent and arranged adjacent to each other, a part of the target biological particle is trapped by the supporting segments of the two of the capture arms and is held.

Catcher, capture device, and method for capturing target biological particle

A signal receiving circuit is provided. The signal receiving circuit includes a receiving circuit, an adjustment circuit and a boundary detection circuit. The receiving circuit is configured to receive an input signal. The adjustment circuit is configured to adjust the input signal. The boundary detection circuit is configured to detect a first signal having a first data pattern in the input signal and a second signal having a second data pattern in the input signal. The boundary detection circuit is further configured to detect a gap value between a first signal boundary of the first signal and a second signal boundary of the second signal to reflect a status of the adjustment circuit.

Signal receiving circuit, memory storage device and method for evaluating status of adjustment circuit for adjusting input signal

A calibration method of an equalizer circuit for a memory storage device is disclosed. The calibration method includes: receiving a first signal; adjusting, by the equalizer circuit, the first signal according to a control parameter to output a second signal; generating a first sampling signal according to a first reference signal and the second signal, wherein the first sampling signal reflects data transmitted by the first signal; and generating a second sampling signal according to a second reference signal and the second signal and adjusting the control parameter according to the second sampling signal to calibrate the equalizer circuit, wherein a voltage value of the first reference signal is different from a voltage value of the second reference signal.

Signal receiving circuit, memory storage device and calibration method of equalizer circuit

An equalizer circuit, a memory storage device and a signal adjustment method are disclosed. The equalizer circuit is configured to receive an input signal, a reference voltage signal and a sensing clock signal and generate an error signal. The equalizer circuit is further configured to generate a first adjustment signal and a second adjustment signal according to the error signal. The equalizer circuit is further configured to update a control code from a first control code to a second control code according to at least one of the first adjustment signal and the second adjustment signal and generate an adjustment control signal according to the control code. The equalizer circuit is further configured to generate a feedback control signal according to the adjustment control signal to restore the control code from the second control code to the first control code.

Equalizer circuit, memory storage device and signal adjustment method

A signal receiving circuit, a memory storage device and a signal receiving method are provided. The signal receiving circuit includes an equalizer module, a clock and data recovery (CDR) circuit and a controller. The equalizer module is configured to receive a first signal and compensate the first signal to generate a second signal. The CDR circuit is configured to perform a phase locking on the second signal. The controller is configured to open or close a signal pattern filter of the CDR circuit according to the second signal, wherein the signal pattern filter is configured to filter a signal having a specific pattern in the second signal.

Signal receiving circuit, memory storage device and signal receiving method

A semiconductor device includes a transistor having a source/drain region. A conductive contact is disposed over the source/drain region. A silicide element is disposed below the conductive contact. The silicide element has a non-angular cross-sectional profile. In some embodiments, the silicide element may have an approximately curved cross-sectional profile, for example an ellipse-like profile. The silicide element is formed at least in part by forming an amorphous region in the source/drain region via an implantation process. The implantation process may be a cold implantation process.

Contact silicide having a non-angular profile

A semiconductor device having a high-k gate dielectric, and a method of manufacture, is provided. A gate dielectric layer is formed over a substrate. An interfacial layer may be interposed between the gate dielectric layer and the substrate. A barrier layer, such as a TiN layer, having a higher concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer is formed. The barrier layer may be formed by depositing, for example, a TiN layer and performing a nitridation process on the TiN layer to increase the concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer. A gate electrode is formed over the barrier layer.

Barrier layer for dielectric layers in  semiconductor devices

An equalizer tuning method for a memory storage device is provided according to an exemplary embodiment of the disclosure. The method includes: receiving a first signal; modulating the first signal by a first modulation circuit according to a first type parameter and modulating the first signal by a second modulation circuit according to a second type parameter; detecting a signal eye-width value and a signal eye-height value of the modulated first signal; and adjusting the first type parameter according to the detected signal eye-width value and adjusting the second type parameter according to the detected signal eye-height value.

Equalizer tuning method, signal receiving circuit and a memory storage device

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Taichung, Taiwan

Sheng-Wen Chen