Micron Technology Incorporated

Inotera Memories, Inc.

Sheng-Wei Yang

Tieh-Chiang Wu

Wen-Chieh Wang

Scott E Sills

Kamal M Karda

Kevin J Torek

Si-Woo Lee

Terrence B McDaniel

Lars P Heineck

Yi Fang Lee

Jaydip Guha

Hung-Ming Tsai

Sanjeev Sapra

Ming-Cheng Chang

Cheng-Shun Chen

Ying-Cheng Chuang

Ping-Cheng Hsu

An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.

Array of vertical transistors and method used in forming an array of vertical transistors

A memory device with a dielectric layer or an air gap between contacts and a method of making the same are disclosed. The method comprises a series of steps including forming a plurality of conductive lines having trenches therebetween; forming a contact layer in the trench; and forming a dielectric layer interposed in the contact layer and configured to divide the contact layer into two contacts. The method also comprises removing the dielectric layer to form a space and forming a cap layer over the two contacts to form an air gap therein. The method further comprises forming a second air gap between the conductive line and the two contacts.

Microelectronic devices including two contacts

Method for fabricating a memory device having two contacts

A method for forming a cell contact. A substrate having first and second protruding structures is prepared. An etch stop layer is deposited over the substrate. A sacrificial layer is deposited on the etch stop layer. The sacrificial layer is recessed. Spacers are formed on the top surface of the sacrificial layer. A portion of the sacrificial layer not covered by the spacers is etched away, thereby forming a recess. A gap filling material layer is deposited into the recess. An upper portion of the gap filling material layer and the spacers are removed to expose the top surface of the sacrificial layer. The sacrificial layer is removed to form contact holes. A punch etching process is performed to remove the etch stop layer from bottoms of the contact holes. The contact holes is filled up with a conductive material layer.

Method for forming cell contact

A method of creating a trench having a portion of a bulb-shaped cross-section in silicon is disclosed. The method comprises forming at least one trench in silicon and forming a liner in the at least one trench. The liner is removed from a bottom surface of the at least one trench to expose the underlying silicon. A portion of the underlying exposed silicon is removed to form a cavity in the silicon. At least one removal cycle is conducted to remove exposed silicon in the cavity to form a bulb-shaped cross-sectional profile, with each removal cycle comprising subjecting the silicon in the cavity to ozonated water to oxidize the silicon and subjecting the oxidized silicon to a hydrogen fluoride solution to remove the oxidized silicon. A semiconductor device structure comprising the at least one trench comprising a cavity with a bulb-shaped cross-sectional profile is also disclosed.

Methods of forming bulb-shaped trenches in silicon

A method of forming a conductive contact includes forming a structure comprising an upper surface joining with a sidewall surface. The sidewall surface contains elemental-form silicon. Silicon is epitaxially grown from the sidewall surface. Dielectric material is formed over the upper surface and the epitaxially-grown silicon. A conductive contact is formed through the dielectric material to conductively connect with the upper surface.

Methods of forming conductive contacts in the fabrication of integrated circuitry

Growing community of inventors

Boise, ID, United States of America

Sheng-Wei Yang