Micron Technology Incorporated

Other

Sheng Wei Yang

Shams U Arifeen

Hyunsuk Chun

Dominik J Schmidt

Keizo Kawakita

Yen-Chun Yeh

Si-Woo Lee

Byung Yoon Kim

Mark A Zaleski

Systems, methods, and apparatus including conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices. One memory device comprises arrays of vertically stacked memory cells, having multiple multi-direction conductive lines arrays of vertically stacked memory cells, including a vertical stack of layers formed from repeating iterations of a group of layers, the group of layers comprising: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer, the second dielectric material layer having a conductive line formed in a horizontal plane therein, and the vertical stack of layers having multiple multi-direction conductive lines in an interconnection region with a first portion of the interconnection region formed in an array region and a second portion formed in a conductive line contact region that is spaced from the array region.

Conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices

Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.

Semiconductor devices having crack-inhibiting structures

Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material&#x2014;such as a low-&#x3ba; dielectric material&#x2014;at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad.

Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material&#x2014;such as a low-&#x3ba; dielectric material&#x2014;at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.

Various embodiments of the invention provide systems and methods for low-cost, low-power Array Waveguide Grating (AWG)-based miniaturized Raman spectroscopy for use in non-invasive glucose monitoring systems, such as in wearable devices that require no replenishment of chemicals or enzymes. The AWG may be manufactured using VLSI processing technology, which significantly reduces manufacturing cost and replaces holographic grating as the dispersive component of light. In embodiments, the AWG is integrated with a number of PIN photodiode detectors on a substrate to further reduce cost and signal loss. In embodiments, a prism-coupling method eliminates alignment problems associated with traditional approaches that utilize fiber-coupling methods.

Arrayed waveguide grating (AWG)-based Raman spectroscopy for glucose monitoring

Presented are systems and methods that perform noninvasive glucose monitoring using mid-infrared self-emission of the human body that acts as a background radiation emitter. Various embodiments accomplish this by taking advantage of the guided-mode resonance (GMR) effect in a number of bandpass filters that are constructed as an array of coplanar filters. The filter array acts as a spectral separator that uses a grating layer and a thin film waveguide to form reflection and transmission filters for particular wavelengths. Unlike, common multi-layer optical filter designs that utilize numerous individual optical filters, a novel GMR filter design comprises an array of filters that may be fabricated from CMOS-compatible materials using only a few thin film and grating layers to filter light. Advantageously, this reduces manufacturing cost and allows for simultaneous monitoring of a number of wavelengths of the glucose spectrum.

Growing community of inventors

Boise, ID, United States of America

Sheng Wei Yang