Taiwan Semiconductor Manufacturing Comp. Ltd.

Sheng-Hsiang Chiu

Ching-Hua Hsieh

Sheng-Feng Weng

Chih-Wei Lin

Chung-Shi Liu

Meng-Tse Chen

Chia-Min Lin

Yao-Tong Lai

Ming-Da Cheng

Yi-Da Tsai

Wei-Hung Lin

Chao-Wen Shih

Han-Ping Pu

Albert Wan

Chao-Wei Li

Yu-Hao Chen

Wei-Lun Tsai

Kai-Ming Chiang

Chen-Hua Douglas Yu

Hsin-Yu Pan

Chin-Yu Ku

Chin-Liang Chen

Kuan-Lin Ho

Yu-Chih Liu

Yu-Peng Tsai

Ta-Jen Yu

Hsiu-Mei Yu

Shing-Chao Chen

Tzu-Ting Chou

Chun-Ying Lin

Young-Chang Lien

A molded semiconductor device includes a semiconductor device and a molding material encapsulating the semiconductor device, wherein an upper surface of the molding material is substantially coplanar with an upper surface of the semiconductor device and comprises a groove at least partially surrounding the upper surface of the semiconductor device.

Molded semiconductor device and manufacturing method of molded semiconductor device

A package structure including a substrate, a first semiconductor element disposed on and electrically connected with the substrate, a second semiconductor element disposed on and electrically connected with the substrate and a molding layer disposed over the substrate and covering at least a top surface of the substrate. The second semiconductor element and the first semiconductor element perform different functions. The molding layer encapsulates the second semiconductor element and wraps around sidewalls of the first semiconductor element. A top surface of the molding layer is higher than a top surface of the first semiconductor element. The molding layer has an opening extending from the top surface of the molding layer to the top surface of the first semiconductor element, so that the top surface of the first semiconductor element is exposed.

Package structure and manufacturing method thereof

Three-dimensional integrated circuit (3DIC) structures and methods of forming the same are provided. A 3DIC structure includes a semiconductor package, a first package substrate, a molded underfill layer and a thermal interface material. The semiconductor package is disposed over and electrically connected to the first package substrate through a plurality of first bumps. The semiconductor package includes at least one semiconductor die and an encapsulation layer aside the semiconductor die. The molded underfill layer surrounds the plurality of first bumps and a sidewall of the semiconductor package, and has a substantially planar top surface. The CTE of the molded underfill layer is different from the CTE of the encapsulation layer of the semiconductor package. The thermal interface material is disposed over the semiconductor package.

Three-dimensional integrated circuit structures and methods of forming the same

A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Package structure

A semiconductor device including a chip package, a dielectric structure, and a first antenna pattern is provided. The dielectric structure is disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern is disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern.

Semiconductor device having antenna and manufacturing method thereof

A molding apparatus is configured for molding a semiconductor device and includes a lower mold and an upper mold. The lower mold is configured to carry the semiconductor device. The upper mold is disposed above the lower mold for receiving the semiconductor device and includes a mold part and a dynamic part. The mold part is configured to cover the upper surface of the semiconductor device. The dynamic part is disposed around a device receiving region of the upper mold and configured to move relatively to the mold part. A molding method and a molded semiconductor device are also provided.

Molding apparatus and manufacturing method of molded semiconductor device

In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.

Advanced info POP and method of forming thereof

Memory device, package structure and fabricating method thereof

Semiconductor device having antenna on chip package and manufacturing method thereof

Molding apparatus, manufacturing method of molded semiconductor device and molded semiconductor device

Advanced INFO POP and method of forming thereof

A semiconductor device including a chip package, a dielectric structure and a first antenna pattern is provided. The dielectric structure disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern. A manufacturing method of a semiconductor device is also provided.

A method includes attaching a first semiconductor package on a carrier, wherein the first semiconductor package comprises a plurality of stacked semiconductor dies and a plurality of contact pads, depositing a first molding compound layer over the carrier, wherein the first semiconductor package is embedded in the first molding compound layer, forming a plurality of vias over the plurality of contact pads, attaching a semiconductor die on the first molding compound layer, depositing a second molding compound layer over the carrier, wherein the semiconductor die and the plurality of vias are embedded in the second molding compound layer, forming an interconnect structure over the second molding compound layer and forming a plurality of bumps over the interconnect structure.

Package-on-package structure and method

Growing community of inventors

Tainan, Taiwan

Sheng-Hsiang Chiu