Taiwan Semiconductor Manufacturing Comp. Ltd.

Mediatek Corporation

Sheng-Fu Hsu

Chen-Liang Chu

Ta-Yuan Kung

Chih-Chung Tsai

Hsiao-Ching Huang

Lin-Yu Huang

Chen-Yi Lee

Hao-Hua Hsu

Chun-Chi Chen

Yu-Chang Jong

Chiu-Hua Chung

Yi-Cheng Chiu

Hsin-Hsien Li

Shih-Fan Chen

Je-Shen Hu

Hao-Shun Chang

Tien-Sheng Lin

Pin-Chen Chen

A semiconductor ESD protection device includes a pair of source regions, a pair of gate structures, a drain region, a plurality of first conductive contacts, a plurality of second conductive contacts, a plurality of third conductive contacts, and a dummy structure. The pair of gate structures are disposed between the pair of source regions and extend along a direction. The drain region is disposed between the pair of gate structures. Each of the first conductive contacts is disposed on one of the pair of source regions and is arranged along the direction. Each of the plurality of second conductive contacts is disposed on one of the pair of gate structures. The plurality of third conductive contacts are disposed on the drain region and arranged along the direction. The dummy structure is disposed over the drain region and between the gate structures and between the third conductive contacts.

Semiconductor electrostatic discharge protection device

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first semiconductor device and second semiconductor device disposed on a semiconductor substrate. The first semiconductor device comprises a first gate structure, a first source region, and a first drain region. The first source and drain regions and are disposed in a first well region. The second semiconductor device comprises a second gate structure, a second source region, and a second drain region. The second source and drain regions are disposed in a second well region. The first and second well regions comprise a first doping type. The first well region is laterally offset from the second well region by a first distance. A third well region is disposed in the semiconductor substrate and laterally between the first and second well regions. The third well region comprises a second doping type opposite the first doping type.

Semiconductor devices with improved layout to increase electrostatic discharge performance

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

Semiconductor device having improved electrostatic discharge protection

The ability of a grounded gate NMOS (ggNMOS) device to withstand and protect against human body model (HBM) electrostatic discharge (ESD) events is greatly increased by resistance balancing straps. The resistance balancing straps are areas of high resistance formed in the substrate between an active area that includes a MOSFET of the ggNMOS device and a bulk ring that surrounds the active area. A Vss rail is coupled to the substrate beneath the MOSFET through the bulk ring. The substrate beneath the MOSFET provides base regions for parasitic transistors that switch on for the ggNMOS device to operate. The straps inhibit low resistance pathways between the base regions and the bulk ring and prevent a large portion of the ggNMOS device from being switched off while a remaining portion of the ggNMOS device remains switched on. The strap may be divided into segments inserted at strategic locations.

Strap technology to improve ESD HBM performance

A semiconductor device is provided. The semiconductor device comprises a substrate of a first type, a first doped region embedded within the substrate and having a first portion and a second portion, and a first gate electrode disposed above the substrate. The semiconductor device further comprises a well region of a second type and embedded within the substrate. The well region is in contact with the second portion of the first doped region.

Transistor drain design for ESD protection and manufacturing method thereof

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a source region and a drain region in a substrate, a gate structure and a metallic line. The source region surrounds the drain region in the substrate. The gate structure is disposed on the substrate, and disposed between the source region and the drain region. The gate structure surrounds the drain region. The metallic line is located above the source and drain regions and the gate structure and electrically connected to the drain region or the source region. The source region includes a doped region having a break region located between two opposite ends of the doped region. The metallic line extends from the drain region, across the gate structure and across the break region and beyond the source region.

Semiconductor device with ring-shaped doped region and manufacturing method thereof

The present disclosure relates to an integrated circuit. The integrated circuit comprises a silicon on insulator (SOI) device separated from a SOI substrate by an insulation layer. The SOI device comprises a power supply terminal, a ground terminal, a first I/O terminal and a second I/O terminal. An electrostatic discharge (ESD) protection circuit is integrated with the SOI device. The ESD protection circuit is configured to shunt current between two terminals of the SOI device during an ESD surge event. An electrostatic discharge (ESD) enhancement circuit is integrated with the SOI device. The ESD enhancement circuit is configured to clamping the SOI substrate to a lower potential of the two terminals of the SOI device.

Integrated ESD enhancement circuit for SOI device

A surge-protection circuit for a chip is provided. The surge-protection circuit includes a detection element and a protection element. The detection element is embedded on the chip and arranged between a first terminal and a second terminal, and the detection element is utilized to detect whether an abrupt voltage variation occurs due to a surge or not and generate an enabling signal when the abrupt voltage variation occurs. The protection element is embedded on the chip and coupled to the detection element, and the protection element is utilized to adjust and reduce the abrupt voltage variation through bypassing high energy generated by the surge after receiving the enabling signal.

Surge-protection circuit and surge-protection method

A signal transceiving circuit comprising an IC including a signal transmitting part. The signal transmitting part comprises: a first I/O pad; a second I/O pad; a first output stage circuit, coupled to the first I/O pad; a second output stage circuit, coupled to the second I/O pad; and a first surge protecting device, comprising a first terminal coupled to the first output stage circuit and the first I/O pad, and comprising a second terminal coupled to the second output stage circuit and the second I/O pad.

Signal receiving circuit and signal transceiving circuit

An output circuit is provided and includes first and second output stage elements, a detection circuit, a control circuit, and a first pre-driver. The first and second output stage elements are coupled in series between a power terminal and the ground terminal. The detection circuit detect whether an electrostatic discharge event occurs at an output terminal between the two output stage elements to generate a control signal. The control circuit controls a state of the first output stage element when the control circuit is enabled according to the control signal. The first pre-driver controls the state of the first output stage element when the first per-driver is enabled according to the control signal. When the detection circuit detects that the electrostatic discharge event occurs at the output terminal, the control circuit is enabled to turn on the first output stage element, and the first pre-driver is disabled.

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Hsinchu, Taiwan

Sheng-Fu Hsu