Taiwan Semiconductor Manufacturing Comp. Ltd.

Global Unichip Corporation

Sheng-Fan Yang

Yuan-Hung Lin

Yu-Cheng Sun

Yi-Tzeng Lin

Wei-Chiao Wang

Chih-Chiang Hung

Yung-Yang Liang

Igor Elkanovich

Hung-Yi Chang

Hao-Yu Tung

Hung-Chang Kuo

Yao-Tsu Chen

Zhong-Yan You

Shih-Hsuan Hsu

Chi-Lou Yeh

Huan-Yi Liao

Steve S A Wan

Chen Lee

A circuit board device includes a multilayer board structure, a main ground and a circuit module. The main ground is configured in the multilayer board structure. The circuit module includes two differential-signal portions. These differential-signal portions are all located on one core layer of the multilayer board structure. Each of the differential-signal portions includes a differential through-hole pair and a plurality of ground through holes, and these ground through holes are arranged at intervals to surround the differential through-hole pair, and are electrically connected to the main ground. The patterns of the differential-signal portions are mirror symmetrical to each other based on an imaginary mirror line therebetween, and the minimum linear distances from the differential-signal portions to the imaginary mirror line are equal to each other.

Circuit board device and its circuit module

A power distribution device includes a substrate, a first chip, a first bump, a second bump and a first capacitor. The first chip is configured to receive a first reference voltage signal and a second reference voltage signal. The first bump is located between the substrate and the first chip, and configured to transmit the first reference voltage signal from the substrate to the first chip. The second bump is located between the substrate and the first chip, and configured to transmit the second reference voltage signal from the substrate to the first chip. The first capacitor is located above the substrate and below the first chip. A first terminal of the first capacitor is coupled to the first bump, and a second terminal of the first capacitor is coupled to the second bump. A power distribution system is also disclosed herein.

Power distribution device, power distribution system and manufacturing method thereof

A semiconductor chiplet device includes a package substrate, an interposer layer, a first die and a second die. The first die includes a first interface, and the second die includes a second interface. A first side of the interposer layer is configured to arrange the first die and the second die. The first die and the second die perform a data transmission through the first interface, the interposer layer and the second interface. The package substrate is arranged on a second side of the interposer layer, and includes a decoupling capacitor. The decoupling capacitor is arranged between the first interface and the second interface, or arranged in a vertical projection area of the first interface and the second interface on the package substrate.

Semiconductor chiplet device

A communication interface structure and a Die-to-Die package are provided. The communication interface structure includes first bumps arranged in a first row-column configuration, second bumps arranged in a second row-column configuration, and conductive lines disposed between the first bumps and the second bumps to connect each of the first bumps to each of the second bumps. The first bumps in neighboring rows are alternately shifted with each other. The second bumps are disposed under or over the first bumps, wherein each of the second bumps in even rows is at a position shifted in a column direction from a center of each of the first bumps in the even rows, and each of the second bumps in odd rows is at a position between two of the second bumps in the even rows in the column direction.

Communication interface structure and Die-to-Die package

An interposer routing structure includes a first trace layer, a bump layer, a second trace layer and a third trace layer. The first trace layer is configured to receive a power. The bump layer is coupled to a die. The second trace layer and the third trace layer are coupled between the first trace layer and the bump layer, and include multiple ground traces and multiple power traces. The ground traces are located on both sides of at least one of the power traces, so that the ground traces isolate the at least one power trace and multiple signal traces. The power traces of the second trace layer are coupled to each other by a connecting power trace, and the ground traces of the third trace layer are coupled to each other by a connecting ground trace.

Interposer routing structure and semiconductor package

A semiconductor wiring substrate includes a first circuit layer, a second circuit layer and a first dielectric layer. The first circuit layer includes a plurality of first signal traces and a plurality of first ground traces, wherein the first signal traces and the first ground traces are alternatively arranged on the first circuit layer, and one of the first signal traces is spaced at a first spacing from adjacent one of the first ground traces. The first dielectric layer is between the first circuit layer and the second circuit layer and has a first thickness in an arrangement direction of the first circuit layer, the first dielectric layer and the second circuit layer, wherein the first spacing substantially ranges from 0.78 to 1.96 times the first thickness.

Semiconductor package device and semiconductor wiring substrate thereof

A power delivery device includes a printed circuit board (PCB), a package device, and a chip connecting device. The PCB is configured to receive a first reference voltage and a second reference voltage. The package device is coupled to the PCB, and includes a bump array. The chip connecting device is coupled to the bump array of the package device, and configured to output a first supply voltage and a second supply voltage. The bump array includes first bumps and second bumps. The first bumps are configured to transmit the first reference voltage. The second bumps are configured to transmit the second reference voltage. The first bumps and the second bumps are disposed in parallel.

Power delivery device and method

A signal transmission device includes a transmission line. The transmission line is configured to receive a signal transmitted from a transmission device, and output the signal to a receiving device. The transmission line includes a signal suppression device. The signal suppression device is coupled to the receiving device, and is configured to suppress a reflection signal reflected from the receiving device. The signal suppression device includes a pull-up element and a compensation element. The pull-up element is configured to decrease an equivalent impedance from the signal suppression device to the receiving device. The compensation element is configured to compensate for the equivalent impedance from the signal suppression device to the receiving device. A first terminal of the pull-up element is coupled to a first terminal of the compensation element, and a second terminal of the compensation element is coupled to the receiving device.

Signal transmission device

A circuit structure including a first signal line and a second signal line is provided. The first signal line includes a first line segment, a first ball grid array pad, and a first through hole disposed between the first line segment and the first ball grid array pad. The second signal line includes a second line segment, a second ball grid array pad, and a second through hole disposed between the second line segment and the second ball grid array pad. In a plan view, a line connecting the center of the first ball grid array pad and the center of the second ball grid array pad has a first distance, a line connecting the center of the first through hole and the center of the second through hole has a second distance, and the first distance is less than the second distance. A chip package is also provided.

Circuit structure and chip package

An integrated circuit package element provided includes a chip element and a package module coupled to the chip element. The chip element includes two driving units that are electrically connected to each other. The package module includes a grounding area, two individual power distributed networks and a grounded shielding structure which is completely disposed between the individual power distributed networks, electrically connected to the chip element, and configured to block power noise coupling between the first electric power distribution network and the second electric power distribution network. The grounding area is electrically connected to the individual electric power distribution networks and the grounded shielding structure.

Integrated circuit package element and load board thereof

A conductive transmission line structure includes a first conductive transmission line and a second conductive transmission line. A first segment and a second segment of the first conductive transmission line are respectively disposed adjacent to a third segment and a fourth segment of the second conductive transmission line. Line widths of the first segment and the third segment are respectively smaller than line widths of the second segment and the fourth segment. A spacing between the first segment and the third segment is smaller than a spacing between the second segment and the fourth segment. The first segment and the third segment provide a first impedance, and the second segment and the fourth segment provide a second impedance. The first impedance is smaller than the second impedance. The first and the third signal transmission nodes receive a differential signal pair.

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Hsinchu, Taiwan

Sheng-Fan Yang