Taiwan Semiconductor Manufacturing Comp. Ltd.

Sheng-De Liu

Chung-Yen Chou

Chia-Shiung Tsai

Shih-Chang Liu

Fu-Chih Yang

Ming Chyi Liu

Chi-Ming Chen

Han-Chin Chiu

Cheng-Yuan Tsai

Ming-Chyi Liu

Yao-Chung Chang

Yu-Syuan Lin

Che-Ming Chang

Yuan-Tai Tseng

King-Yuen Wong

Ming-Wei Tsai

Chia-Shiung Tsa

Present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate, forming a first III-V compound layer over the substrate, forming a first passivation layer over the first III-V compound layer, forming a first opening from a top surface of the first passivation layer to the first III-V compound layer, each opening having a stair-shaped sidewall at the first passivation layer, depositing a metal layer over the first passivation layer and in the first opening, the metal layer having a second opening above the corresponding first opening, and removing a portion of the metal layer to form a source electrode and a drain electrode.

Manufacturing method of semiconductor structure

A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.

Semiconductor device containing HEMT and MISFET and method of forming the same

A semiconductor structure includes a semiconductive substrate having a top surface, a III-V compound layer covering the top surface, and a passivation layer having a lower portion and an upper portion, both comprising at least one of oxide and nitride over the III-V compound layer. The semiconductor structure also includes an etch stop layer between the lower portion and the upper portion of the passivation layer, and a gate stack penetrating through the etch stop layer and landing on the lower portion of the passivation layer. The gate stack is surrounded by the etch stop layer.

High-electron-mobility transistor (HEMT) structure capable of protecting a III-V compound layer and manufacturing method thereof

The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V compound layer over the substrate, a first passivation layer on the first III-V compound layer, a source region and a drain region. The source region penetrates the first passivation layer to electrically contact the first III-V compound layer. The drain region penetrates the first passivation layer to electrically contact the first III-V compound layer. A sidewall of the first passivation layer contacting with the source region comprises a stair shape.

Semiconductor structure and manufacturing method thereof

A semiconductor structure comprises a semiconductive substrate comprising a top surface, a III-V compound layer over the semiconductive substrate, and a first passivation layer over the III-V compound layer. The semiconductor structure also includes an etch stop layer over the first passivation layer. The semiconductor structure further includes a gate stack over the first passivation layer and surrounded by the etch stop layer.

High-electron-mobility transistor (HEMT) capable of protecting a III-V compound layer

Embodiments of the present disclosure include a MISFET device. An embodiment includes a source/drain over a substrate, a first etch stop layer on the source/drain, and a gate dielectric layer on the first etch stop layer and along the substrate. The embodiment also includes a gate electrode on the gate dielectric layer, and a second etch stop layer on the gate electrode.

MISFET device

A high-electron mobility transistor (HEMT) device employing a gate protection layer is provided. A substrate has a channel layer arranged over the substrate and has a barrier layer arranged over the channel layer. The channel and barrier layers define a heterojunction, and a gate structure is arranged over a gate region of the barrier layer. The gate structure includes a gate arranged over a cap, where the cap is disposed on the barrier layer. The gate protection layer is arranged along sidewalls of the cap and arranged below the gate between opposing surfaces of the gate and the cap. Advantageously, the gate protection layer passivates the gate, reduces leakage current along sidewalls of the cap, and improves device reliability and threshold voltage uniformity. A method for manufacturing the HEMT device is also provided.

Structure for a gallium nitride (GaN) high electron mobility transistor

Among other things, one or more semiconductor arrangements comprising isolation trenches, and techniques for forming such isolation trenches are provided. A substrate comprises a front side surface and a backside surface. One or more devices are formed over the front side surface. A wet etch is performed to form a tapered portion of an isolation trench. A dry etch is performed to form a non-tapered portion of the isolation trench. Because both the wet etch and the dry etch are performed, etching time is reduced compared to merely using the dry etch due to the wet etch having a relatively faster etch rate than the dry etch. In an embodiment, the isolation trench provides isolation for a current leakage path associated with a device or other material formed over the front side surface. In an embodiment, metal is formed within the isolation trench for backside metallization.

Isolation trench through backside of substrate

Embodiments of the present disclosure include a method for forming a semiconductor device, a method for forming a MISFET device, and a MISFET device. An embodiment is a method for forming a semiconductor device, the method including forming a source/drain over a substrate, forming a first etch stop layer on the source/drain, and forming a gate dielectric layer on the first etch stop layer and along the substrate. The method further includes forming a gate electrode on the gate dielectric layer, forming a second etch stop layer on the gate electrode, and removing the gate dielectric layer from over the source/drain.

MISFET device and method of forming the same

Among other things, one or more wafer edge protection structures and techniques for forming such wafer edge protection structures are provided. A substrate of a semiconductor wafer comprises an edge, such as a beveled wafer edge portion, that is susceptible to Epi growth which results in undesirable particle contamination of the semiconductor wafer. Accordingly, a wafer edge protection structure is formed over the beveled wafer edge portion. The wafer edge protection structure comprises an Epi growth resistant material, such as an amorphous material, a non-crystalline material, oxide, or other material. In this way, the wafer edge protection structure mitigates Epi growth on the beveled wafer edge portion, where the Epi growth increases a likelihood of particle contamination from cracking or peeling of an Epi film resulting from the Epi growth. The wafer edge protection structure thus mitigates at least some contamination of the wafer.

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Zhongli, Taiwan

Sheng-De Liu