Taiwan Semiconductor Manufacturing Comp. Ltd.

Sheng-Chieh Chen

Shih-Chang Liu

Ming Chyi Liu

Yu-Hsing Chang

Chang-Ming Wu

Ming-Chyi Liu

Chih-Ren Hsieh

Wei-Ming Wang

Ming-Lun Lee

Yung-Chang Chang

Yuan-Tai Tseng

Tsung-Hsueh Yang

A semiconductor memory device and method of making the same are disclosed. The semiconductor memory device includes a substrate that includes a memory region and a peripheral region, a transistor including a metal gate located in the peripheral region, a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, where the second dielectric layer has a greater density than a density of the first dielectric layer, and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection of the metal gate against etching damage and thereby improves device performance.

Semiconductor memory device having composite dielectric film structure and methods of forming the same

A semiconductor device includes a substrate, an isolation feature, a floating gate, and a control gate. The substrate has a protruding portion. The isolation feature surrounds the protruding portion of the substrate. The floating gate is over the protruding portion of the substrate, in which a sidewall of the floating gate is aligned with a sidewall of the protruding portion of the substrate. The control gate is over the floating gate.

Semiconductor device and manufacturing method thereof

Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

Cell boundary structure for embedded memory

Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.

Flash memory with improved gate structure and a method of creating the same

A process is provided to fabricate a finFET device. A gate electrode layer is positioned over a dielectric layer. The gate electrode layer and the dielectric layer are both positioned over and surrounding a fin-shaped semiconductor structure. A gate electrode is formed from the gate electrode layer through a two-step patterning process. At a first patterning step, an upper portion of the gate electrode layer is patterned. Then a dielectric film is formed covering the patterned upper portion of the gate electrode layer. After the dielectric film is formed, a second patterning process is performed to pattern a lower portion of gate electrode layer.

Forming fin-FET semiconductor structures

An integrated circuit for a flash memory device with enlarged spacing between select and memory gate structures is provided. The enlarged spacing is obtained by forming corner recesses at the select gate structure so that a top surface with a reduced dimension of the select gate structure is obtained. In one example, a semiconductor substrate having memory cell devices formed thereon, the memory cell devices include a semiconductor substrate having memory cell devices formed thereon, the memory cell devices includes a plurality of select gate structures and a plurality of memory gate structures formed adjacent to the plurality of select gate structures, wherein at least one of the plurality of select gate structures have a corner recess formed below a top surface of the at least one of the plurality of select gate structures.

Flash memory structure with reduced dimension of gate structure and methods of forming thereof

A method for forming a semiconductor memory device structure includes forming a select gate structure and a dielectric layer, forming a charge trapping layer along a sidewall of a lower portion of the select gate structure and a sidewall of the dielectric layer, and forming a memory gate structure over the charge trapping layer. The select gate structure and the memory gate structure contact opposing sidewalls of the charge trapping layer. The dielectric layer is interposed between the charge trapping layer and the select gate structure.

An integrated circuit for a flash memory device with enlarged spacing between select and memory gate structures is provided. The enlarged spacing is obtained by forming corner recesses at the select gate structure so that a top surface with a reduced dimension of the select gate structure is obtained. In one example, a semiconductor substrate having memory cell devices formed thereon, the memory cell devices includes a semiconductor substrate having memory cell devices formed thereon, the memory cell devices includes a plurality of select gate structures and a plurality of memory gate structures formed adjacent to the plurality of select gate structures, wherein at least one of the plurality of select gate structures have a corner recess formed below a top surface of the at least one of the plurality of select gate structures.

Flash memory structure with reduced dimension of gate structure

The present disclosure relates to an improved integrated circuit having an embedded flash memory device with a word line having its height reduced, and associated processing methods. In some embodiments, the flash memory device includes a gate stack separated from a substrate by a gate dielectric. The gate stack includes a control gate separated from a floating gate by a control gate dielectric. An erase gate is disposed on a first side of the gate stack and a word line is disposed on a second side of the gate stack that is opposite to the first side. The word line has a height that monotonically increases from an outer side opposite to the gate stack to an inner side closer to the gate stack. A word line height at the outer side is smaller than an erase gate height.

Self-aligned flash memory device

Some embodiments of the present disclosure relate to a flash memory device. The flash memory device includes first and second individual source/drain (S/D) regions spaced apart within a semiconductor substrate. A common S/D region is arranged laterally between the first and second individual S/D regions, and is separated from the first individual S/D region by a first channel region and is separated from the second individual S/D region by a second channel region. An erase gate is arranged over the common S/D. A floating gate is disposed over the first channel region and is arranged to a first side of the erase gate. A control gate is disposed over the floating gate. A wordline is disposed over the first channel region and is spaced apart from the erase gate by the floating gate and the control gate. An upper surface of the wordline is a concave surface.

Growing community of inventors

Taichung, Taiwan

Sheng-Chieh Chen