Taiwan Semiconductor Manufacturing Comp. Ltd.

Powertech Technology Inc.

Sheng-Chi Lin

Tsung-Min Lin

Fang-Chi Chien

Shin-Kung Chen

Jui-Feng Jao

Kun-Chih Chan

Lung-Yin Tang

An insulator for an ion implantation source may provide electrical insulation between high voltage components and relatively lower voltage components of the ion implantation source. To reduce the likelihood of and/or prevent a leakage path forming along the insulator, the insulator may include an internal cavity having a back and forth pattern. The back and forth pattern of the internal cavity increases the mean free path of gas molecules in the ion implantation source and increases the surface area of the insulator that is not directly or outwardly exposed to the gas molecules. This results in a continuous film or coating being more difficult and/or less likely to form along the insulator, which extends the working time of the ion implantation source.

Insulator for an ion implantation source

Disclosed is a wafer level testing method for testing a plurality of singulated 3D-stacked chip cubes by utilizing adjustable wafer maps to adjust the pick-and-place positions of the cubes on a carrier wafer. The wafer maps have a plurality of probe-card activated regions each including a plurality of component-attaching regions. Two wafer-level testing steps are performed on the cubes disposed on the carrier wafer according to the wafer maps. By analyzing the electrical testing results of the trial-run wafer-level testing step from the original wafer map, some prone-to-overkill component-attaching regions are confirmed and to create a corrected wafer map which the prone-to-overkill component-attaching regions are excluded from probe-card activated regions. Then, according to the corrected wafer map, cubes are disposed on the carrier wafer without disposing in the prone-to-overkill component-attaching regions. Accordingly, the real-production wafer-level testing step can be run smoothly without unnecessary shut down of adjustment or repair leading to the maximum productivity without overkill issues.

Wafer-level testing method for singulated 3D-stacked chip cubes

Growing community of inventors

Hsinchu, Taiwan

Sheng-Chi Lin