Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

Sheng-Chen Chung

Kong-Beng Thei

Harry Chuang

Bao-Ru Young

Harry-Hak-Lay Chuang

Lee-Wee Teo

Chiung-Han Yeh

Yu-Ying Hsu

Mong-Song Liang

Chung Long Cheng

Ming Zhu

Wei Cheng Wu

Jung-Hui Kao

Hak-Lay Chuang

Tzung-Chi Lee

Chung-Long Cheng

Harry Hak-Lay Chuang

Mong Song Liang

Shun-Jang Liao

Kai-Shyang You

Huan-Just Lin

Chih-Chung Wang

Jin-Aun Ng

Chiu-Te Lee

Wen-Huei Guo

Jyun-Ming Lin

Tsai-Chun Li

Chen-An Kuo

Chi-Ju Lee

Hsien-Wei Chen

Shin-Puu Jeng

Hao-Yi Tsai

Carlos H Diaz

Wei-Cheng Wu

Ryan Chia-Jen Chen

Yi-Ming Sheu

Po-Nien Chen

Ke-Feng Lin

Gwan Sin Chang

Kuang-Hsiu Chen

Chia Ming Liang

Gary Shen

Sin-Hua Wu

Chih-Tsung Yao

Liang-An Huang

Yuan-Cheng Yang

Chun-Lin Chen

Yi-Han Su

Yan-Huei Li

Kai-Ting Hu

Anson Wang

Hsiang-Hua Hsu

The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Polysilicon design for replacement gate technology

A metal-oxide-semiconductor (MOS) transistor includes a substrate. The substrate has a plurality of trenches extending along a first direction and located on a top portion of the substrate. A gate structure line is located on the substrate and extends along a second direction intersecting with the first direction and crossing over the trenches. A first doped line is located in the substrate, located at a first side of the gate structure line, and crosses over the trenches. A second doped line is located in the substrate, located at a second side of the gate structure line, and crosses over the trenches.

Metal-oxide-semiconductor transistor and method of fabricating the same

A gate oxide forming process includes the following steps. A substrate including a first area and a second area is provided. A first oxide layer, a silicon containing cap layer and a second oxide layer on the substrate of the first area and the second area are sequentially and blanketly formed. The silicon containing cap layer and the second oxide layer in the first area are removed. An oxidation process is performed to oxidize the silicon containing cap layer and a gate oxide layer is formed in the second area.

Gate oxide forming process

A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

Device for high-K and metal gate stacks

A method of preventing contact metal from protruding into neighboring gate devices to affect work functions of the neighboring gate devices is provided includes forming a gate structure. Forming the gate structure includes forming a work function layer, and forming a gate metal layer having a void, wherein the work function layer surrounds the gate metal layer. The method further includes forming a contact plug having a contact metal directly on the gate metal layer of the first gate stack, wherein the contact metal protrudes into the void, and the work function layer prevents the contact metal from protruding into a second gate stack.

Methods to stop contact metal from extruding into replacement gates

The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having an active region; at least one operational device on the active region, wherein the operational device include a strained channel; and at least one first dummy gate disposed at a side of the operational device and on the active region.

Method for mechanical stress enhancement in semiconductor devices

A method of semiconductor device fabrication including providing a substrate having a gate dielectric layer such as a high-k dielectric disposed thereon. A tri-layer element is formed on the gate dielectric layer. The tri-layer element includes a first capping layer, a second capping layer, and a metal gate layer interposing the first and second capping layer. One of an nFET and a pFET gate structure are formed using the tri-layer element, for example, the second capping layer and the metal gate layer may form a work function layer for one of an nFET and a pFET device. The first capping layer may be a sacrificial layer used to pattern the metal gate layer.

Method of fabricating a metal gate semiconductor device

A method includes forming a PMOS device. The method includes forming a gate dielectric layer over a semiconductor substrate and in a PMOS region, forming a first metal-containing layer over the gate dielectric layer and in the PMOS region, performing a treatment on the first metal-containing layer in the PMOS region using an oxygen-containing process gas, and forming a second metal-containing layer over the first metal-containing layer and in the PMOS region. The second metal-containing layer has a work function lower than a mid-gap work function of silicon. The first metal-containing layer and the second metal-containing layer form a gate of the PMOS device.

CMOS devices with metal gates and methods for forming the same

A process fabricating a semiconductor device with a hybrid HK/metal gate stack fabrication is disclosed. The process includes providing a semiconductor substrate having a plurality of isolation features between a PFET region and a NFET region, and forming gate stacks on the semiconductor substrate. In the PFET region, the gate stack is formed as a HK/metal gate. In the NFET region, the gate stack is formed as a polysilicon gate. A high-resistor is also formed on the semiconductor substrate by utilizing another polysilicon gate.

Method of hybrid high-k/metal-gate stack fabrication

Growing community of inventors

Jhubei, Taiwan

Sheng-Chen Chung