Taiwan Semiconductor Manufacturing Comp. Ltd.

Sheng-Chau Chen

Cheng-Hsien Chou

Cheng-Yuan Tsai

Sheng-Chan Li

Yeur-Luen Tu

Hsun-Chung Kuang

Dun-Nian Yaung

Kuo-Ming Wu

Feng-Chi Hung

Chih-Hui Huang

Shih Pei Chou

Ming-Che Lee

Chia-Shiung Tsai

Ching-Chun Wang

Yung-Lung Lin

Cheng-Tai Hsiao

Min-Feng Kao

Hau-Yi Hsiao

Jen-Cheng Liu

Chun-Chieh Chuang

Chih-Yu Lai

Chin-Wei Liang

Yen-Chang Chu

Shyh-Fann Ting

Yao-Wen Chang

Sin-Yao Huang

Zhi-Yang Wang

Shih-Pei Chou

Wen-Chang Kuo

I-Nan Chen

Chung-Liang Cheng

Tzu-Hsuan Hsu

Jeng-Shyan Lin

Cheng-Ta Wu

Chun-Wei Chang

Xiaomeng Chen

Shu-Ting Tsai

Hsiao-Hui Tseng

Tsun-Kai Tsao

Ming-Tung Wu

Wei-Cheng Hsu

Chun-Han Tsao

Kai-Chun Hsu

Chia-Chieh Lin

Tung-He Chou

Che Wei Yang

Chih-Ta Chen

Alexander Kalnitsky

Pinyen Lin

Chung-Yi Yu

Huang-Lin Chao

Feng-Jia Shiu

Yeong-Jyh Lin

Tzu-Jui Wang

Ching-Sen Kuo

Kuan-Liang Liu

Wei-Chieh Huang

Cheng-Ying Ho

Jieh-Jang Chen

Ping-Tzu Chen

Tsai-Ming Huang

Cheng-Che Chung

Xiao-Meng Chen

Ju-Shi Chen

Hui-Wen Shen

Chih Cheng Shih

Paul Yang

Kuo-Cheng Lee

Yun-Wei Cheng

Chun-Hao Chou

Jhy-Jyi Sze

Ming Chyi Liu

Ru-Liang Lee

Chung-Jen Huang

Chia-Yu Wei

Kuo-Hwa Tzeng

Ming-Hsien Yang

Chao-Ching Chang

Tung-Ting Wu

Kuo Liang Lu

Chih-Lung Cheng

Guanyu Luo

Chun-Kai Lan

Tsung-Wei Huang

Yen-Chang Chen

Chun Liang Chen

Feng-chi Hung

Wen-Jen Tsai

Yu Jiang

Chih-Cheng Shih

Cheng Han Lin

Yu-Hsun Chih

Ming-Jhe Lee

Yu-Min Chen

Some implementations described herein include systems and techniques for fabricating a wafer-on-wafer product using a filled lateral gap between beveled regions of wafers included in a stacked-wafer assembly and along a perimeter region of the stacked-wafer assembly. The systems and techniques include a deposition tool having an electrode with a protrusion that enhances an electromagnetic field along the perimeter region of the stacked-wafer assembly during a deposition operation performed by the deposition tool. Relative to an electromagnetic field generated by a deposition tool not including the electrode with the protrusion, the enhanced electromagnetic field improves the deposition operation so that a supporting fill material may be sufficiently deposited.

Semiconductor processing tool and methods of operation

Some implementations described herein include systems and techniques for fabricating a stacked die product. The systems and techniques include using a supporting fill mixture that includes a combination of types of composite particulates in a lateral gap region of a stack of semiconductor substrates and along a perimeter region of the stack of semiconductor substrates. One type of composite particulate included in the combination may be a relatively smaller size and include a smooth surface, allowing the composite particulate to ingress deep into the lateral gap region. Properties of the supporting fill mixture including the combination of types of composite particulates may control thermally induced stresses during downstream manufacturing to reduce a likelihood of defects in the supporting fill mixture and/or the stack of semiconductor substrates.

Composite particulates for use as part of a supporting fill mixture in a semicondutor substrate stacking application

A stacked CMOS image sensor (CIS) structure is provided. The stacked CIS structure comprises a first die, a second die and a third die. The first die comprises a photodiode, a transfer gate, a selective conversion gain (SCG) switch, a reset switch, a floating node diffusion capacitor and a SCG diffusion capacitor. The second die comprises a source follower transistor and a row select switch. The third die comprises an image sensing circuit electrically connected to the third floating node.

Multi-wafer stacked CMOS image sensor structure

Some embodiments relate to an image sensor. The image sensor includes a semiconductor substrate including a pixel region and a peripheral region. A backside isolation structure extends into a backside of the semiconductor substrate and laterally surrounds the pixel region. The backside isolation structure includes a metal core, and a dielectric liner separates the metal core from the semiconductor substrate. A conductive feature is disposed over a front side of the semiconductor substrate. A through substrate via extends from the backside of the semiconductor substrate through the peripheral region to contact the conductive feature. The through substrate via is laterally offset from the backside isolation structure. A conductive bridge is disposed beneath the backside of the semiconductor substrate and electrically couples the metal core of the backside isolation structure to the through substrate via.

Stacked structure for CMOS image sensors

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes bonding a first semiconductor wafer to a second semiconductor wafer. A bond interface is disposed between the first and second semiconductor wafers. The first semiconductor wafer has a peripheral region laterally surrounding a central region. A support structure is formed between a first outer edge of the first semiconductor wafer and a second outer edge of the second semiconductor wafer. The support structure is disposed within the peripheral region. A thinning process is performed on the second semiconductor wafer.

Support structure to reinforce stacked semiconductor wafers

In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.

Semiconductor device and methods of manufacturing thereof

In some embodiments, the present disclosure relates to an image sensor. The image sensor comprises a substrate. A photodetector is in the substrate and includes a semiconductor guard ring extending into a first side of the substrate. A shallow trench isolation (STI) structure extends into the first side of the substrate. An outer isolation structure extends into a second side of the substrate, opposite the first side of the substrate, to the STI structure. The STI structure and the outer isolation structure laterally surround the photodetector. An inner isolation structure extends into the second side of the substrate and overlies the photodetector. The inner isolation structure is vertically separated from the photodetector by the substrate. Further, the outer isolation structure laterally surrounds the inner isolation structure.

Image sensor with dual trench isolation structure

A tunable plasma exclusion zone in semiconductor fabrication is provided. A semiconductor wafer is provided within a chamber of a plasma processing apparatus between a first plasma electrode and a second plasma electrode. A plasma is generated from a process gas within the chamber and an electric field between the first plasma electrode and the second plasma electrode. The plasma is at least partially excluded from an edge region of the semiconductor wafer by a plasma exclusion zone (PEZ) ring within the chamber. The plasma may be tuned toward a center of the semiconductor wafer by electrically coupling an electrode ring of the PEZ ring to a voltage potential.

Tunable plasma exclusion zone in semiconductor fabrication

A method of fabricating a semiconductor device includes receiving a device substrate; forming an interconnect structure on a front side of the device substrate; and etching a recess into a backside of the device substrate until a portion of the interconnect structure is exposed. The recess has a recess depth and an edge of the recess is defined by a sidewall of the device substrate. A conductive bond pad is formed in the recess, and a first plurality of layers cover the conductive bond pad, extend along the sidewall of the device substrate, and cover the backside of the device substrate. The first plurality of layers collectively have a first total thickness that is less than the recess depth. A first chemical mechanical planarization is performed to remove portions of the first plurality of layers so remaining portions of the first plurality of layers cover the conductive bond pad.

Bond pad structure for bonding improvement

In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first integrated chip (IC) tier and a second IC tier. The second IC tier comprises a second plurality of conductors within a second insulating structure disposed on the second semiconductor body. A conductive pad is electrically coupled to the second plurality of conductors and has a conductive surface available to a side of the second semiconductor body facing away from the first semiconductor body. The IC first tier contacts the second IC tier along a bonding interface including one or more conductive regions and one or more insulating regions. The one or more conductive regions laterally outside of a bottom surface of the conductive pad.

Hybrid bond pad structure

Some embodiments relate to a semiconductor structure. The semiconductor structure includes a conductive structure over a semiconductor substrate. A first dielectric layer is over the conductive structure. A second dielectric layer is over the first dielectric layer. An interconnect structure is over the conductive structure and disposed in the first and second dielectric layers. The interconnect structure has a protrusion in direct contact with a sidewall of the conductive structure. The interconnect structure comprises an interconnect liner surrounding a conductive interconnect body. A sidewall spacer is disposed on the sidewall of the conductive structure.

Conductive structure connection with interconnect structure

The present disclosure relates to a semiconductor wafer structure including a semiconductor substrate and a plurality of semiconductor devices disposed along the semiconductor substrate. A dielectric stack including a plurality of dielectric layers is arranged over the semiconductor substrate. A conductive interconnect structure is within the dielectric stack. A seal ring layer is over the dielectric stack and laterally surrounds the dielectric stack along a first sidewall of the dielectric stack. The seal ring layer includes a first protrusion that extends into a first trench in the semiconductor substrate.

Semiconductor wafer seal ring having protrusion extending into trench in semiconductor substrate

Various embodiments of the present disclosure are directed towards an image sensor having a semiconductor substrate comprising a front-side surface opposite a back-side surface. A plurality of photodetectors is disposed in the semiconductor substrate. An isolation structure extends into the back-side surface of the semiconductor substrate and is disposed between adjacent photodetectors. The isolation structure includes a metal core, a conductive liner disposed between the semiconductor substrate and the metal core, and a first dielectric liner disposed between the conductive liner and the semiconductor substrate. The metal core comprises a first metal material and the conductive liner comprises the first metal material and a second metal material different from the first metal material.

High reflectance isolation structure to increase image sensor performance

A thin-film deposition system includes a top plate positioned above a wafer and configured to generate a plasma during a thin-film deposition process. The system includes a gap sensor configured to generate sensor signals indicative of a gap between the wafer and the top plate. The system includes a control system configured to adjust the gap during the thin-film deposition process responsive to the sensor signals.

Method and system for adjusting the gap between a wafer and a top plate in a thin-film deposition process

In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

Embedded backside memory on a field effect transistor

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Tainan, Taiwan

Sheng-Chau Chen