Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Hewlett-packard Development, L.p.

Apache Design Solutions, Inc.

Shen Lin

Norman H Chang

Weize Xie

Osamu Samuel Nakagawa

John G McBride

Keunmyung Lee

Richard M Chou

Osamn S Nakagawa

Xuejue Huang

O Samual Nakagawa

Kenynmyung Lee

Yu Cao

An efficient inductance modeling approach for on-chip power-ground wires using their effective self-loop-inductances is disclosed. Instead of extracting the inductive coupling between every two parallel wires and putting this huge number inductance elements into circuit simulation, this technique determines the effective self-loop-inductance for each power or ground wire segment and only generates a circuit with these effective self-inductors for simulation. This approach greatly reduces the circuit size and makes the full-chip power-ground simulation with the consideration of inductance feasible.

On-chip power-ground inductance modeling using effective self-loop-inductance

A system and method to reduce leakage power consumption of electronic devices. In addition to assigning threshold voltages, sizes of the transistors within the device may be varied to provide a range of options to meet the timing requirements while minimizing the leakage power consumption.

System and method to reduce leakage power in an electronic device

A method determines a plurality of clock delay values. Each delay value is associated with a delay element on a clock line leading to a clock sink in a synchronous circuit. The method determines an initial set of delay values and executes an optimization algorithm, beginning with the initial set of delay values, to arrive at a set of delay values that at least approximately meets an criteria while satisfying timing constraints associated with selected pairs of logically connected clock sinks. In a preferred form, the optimization algorithm is a genetic algorithm or a gradient descent algorithm. The genetic algorithm involves selecting parent sets of delay values, crossing over so as to produce a child set of delay values, mutating the child set of delay values, evaluating how well the child set of delay values meets the criteria, and conditionally discarding the child set on the basis of the evaluating step. The gradient descent algorithm involves perturbing the initial set of delay values, evaluating how well the perturbed set of delay values meets the criteria, and conditionally discarding the perturbed set on the basis of the evaluating step. If the perturbed set is not discarded, then the gradient descent algorithm adjusts the values of the perturbed set in the same direction relative to the corresponding values in the initial set.

System and method for determining a plurality of clock delay values using an optimization algorithm

A method reduces noise resulting from a current surge in a circuit. A plurality of loading elements, parallel with the circuit being protected, are connected sequentially and disconnected. The connection of the loading elements results in a ramping up of current through the circuit without a sudden surge. In a preferred embodiment, an apparatus for slowing a current change in a circuit is described. The apparatus comprises a plurality of loading elements placed in parallel with the circuit, each of the elements providing a path for current flow, and a control circuit for selectively opening or closing at least one of said paths to prevent or enable current flow through the at least one of the paths.

Method for reducing current surge using multi-stage ramp shunting

A logic gate circuit and related methods and apparatus exhibit reduced voltage swing and thereby consume less power. The circuit is connected to a plurality of input signals and a clock signal. The circuit produces an output. The circuit comprises a node, a pull-down network and an N-type MOS transistor. The pull-down network is connected to the node, a first reference voltage, the plurality of inputs and the clock signal. The N-type MOS transistor is connected between the node and a second reference voltage. The N-type MOS transistor is also connected to a complement of the clock signal. A method of the invention accepts a complement of a clock signal and pre-charges a node to a voltage less than a power supply voltage, in response to the complement of the clock signal. The method also accepts a plurality of input signals and accepts the clock signal. The method conditionally discharges the node, in response to the clock signal, on the basis of the plurality of input signals.

Partial swing low power CMOS logic circuits

A system and method is provided for controlling clock skew to meet timing constraints for a semiconductor integrated circuit. On-chip self-tuning circuits can be connected to each latch in the integrated circuit for controlling clock skew. Each self-tuning circuit delays a clock signal that is input to a latch when the clock skew does not satisfy the timing constraint for that latch. The self-tuning circuit repeatedly delays the clock signal until the clock skew is satisfied or until the delay becomes greater than or equal to a predetermined threshold. The delayed clock signal is then pushed to other latches in the integrated circuit until all the timing constraints for the integrated circuit are satisfied.

Parallel push algorithm detecting constraints to minimize clock skew

An RLC module is configured to provide a simplified circuit modeling of a selected circuit net (or portion) of an electronic circuit. The RLC module may be configured to substitute an RLC circuit model for the selected circuit net, where the effective values of the capacitance and inductance for the RLC circuit model are retrieved from a table of capacitance and inductance values. A set of interconnect geometry factors (e.g., line length, line width, driver/receiver length, etc.) that describes the circuit net is used as an index into the table of capacitance and inductance values. The retrieved values of the effective capacitance and inductances values may be used to calculate a delay for the RLC circuit model. The RLC module may provide the capability to quickly calculate a delay for a selected circuit net without using computationally intensive calculations for inductance and capacitance values of circuit nets.

System for improving circuit simulations by utilizing a simplified circuit model based on effective capacitance and inductance values

A method is disclosed for estimating inductive coupling noise of a signal on a transmission line in a circuit design stored in a computer memory. The method determines the capacitive coupling noise on the signal, adds inductive coupling noise, and compares the total to a specified maximum amount of noise. The inductive coupling is a percentage of a supply voltage, which percentage varies depending upon the transition rate of the signal, the resistance of the line, and the gate capacitance of a load on the line. The inductive coupling varies based on the circuit design and may be stored in a table having inductive coupling values for multiple design conditions. The table is created using a field solver to determine line characteristics and a circuit simulator to simulate inductive coupling noise. For each set of initial conditions, a worst-case inductive coupling value is recorded in the table.

Method and system for screening a VLSI design for inductive coupling noise

A method of operating a data processing system to estimate the inductance values associated with a first metal trace having a defined width, thickness, and length in an integrated circuit. In the present invention, the number and location of any ground planes that are adjacent to the first trace in the integrated circuit are first determined. A first current loop passing through the first trace that depends on the number and location of the ground planes, if any, is defined. The magnetic flux per unit area generated in the first current loop when a predetermined current passes through the first trace is then determined and used to estimate the self-inductance of the first trace. If the first trace is adjacent to any ground planes, current loops through the first trace and the ground planes are also defined. The mutual inductance of the first trace and a second trace parallel thereto is determined by defining a current loop that passes through the first and second traces and determining the magnetic flux per unit area generated in the current loop when a predetermined current flows through the first trace. If the first trace and the second trace are adjacent to ground planes, additional current loops passing through each ground plane and one of the first and second traces are also defined. The invention reduces the computational workload inherent in extracting inductance by substituting N two-trace problems for the general problem involving N parallel traces.

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Foster City, CA, United States of America

Shen Lin