National Taiwan University

National Science Council

Mediatek Corporation

Novatek Microelectronics Corp.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Archic Tech. Corp.

Realtek Semiconductor Inc.

Faraday Technology Corporation

Mediatek Incorporation

Sitronix Technology Corporation

National Science Council of Republic of China

Shen-Iuan Liu

Jing-Shown Wu

Chih-Hung Lee

Chewn-Pu Jou

Fu-Lung Hsueh

Ju-Lin Huang

Tzu-Chien Tzeng

Hen-Wai Tsao

You-Jen Wang

Hsiang-Hui Chang

Keko-Chun Liang

Che-Wei Yeh

Ching-Yuan Yang

Yu-Hsiang Wang

Chorng-Kuang Wang

Che-Fu Liang

Feng Wei Kuo

Feng-Wei Kuo

Ka-Un Chan

Hsieh-Hung Hsieh

Liang-Gee Chen

Yen-Jen Chen

Peng-Yu Chen

Gin-Kou Ma

Yu-Che Yang

Tzu-Yi Yang

Jin-Yi Lin

Yong-Ren Fang

Chih-Hao Sun

Yao-Hung Kuo

Chia-Liang Lai

Yen-Long Lee

Sy-Chyuan Hwu

Kun-Yin Wang

Lan-Chou Cho

Chih-Hao Huang

Poki Chen

Chien-Hung Kuo

I-Ting Lee

Kuo-Sheng Huang

Cheng-En Hsieh

Sao-Hung Lu

Kun-Hsun Liao

Ruey-Yuan Tsai

Hen-Wei Tsao

Tzong-Bang Yu

Shuo-Chun Chou

Yun-Sheng Yao

Hsi-Han Chiang

Tao-Yao Chang

Yong-Ru Lu

Yun-Ta Tsai

Sheng-You Lin

I-Fong Chen

Mu-Chen Huang

Jung-Yu Chang

Chao-Ching Hung

Che-Wei Fan

Yuh-Shang Hwang

Ding-Shiuan Shen

Chang-Cheng Huang

Shao-Ku Kao

Chia-Hsin Wu

Tzu-Chien Hsueh

Jian-Ming Yang

Cheng-Chieh Chang

Poko Chen

Jing-Shawn Wu

The present invention provides a sub-sampling PLL including a first phase detector, a first charge pump, an oscillator and a first buffer is disclosed. In the operations of the sub-sampling PLL, the first phase detector uses a reference clock signal to sample a feedback signal to generate a first phase detection result, the first charge pump generates a first signal according to the first phase detection result and a pulse signal, the oscillator generates an output clock signal according to the first signal, and the first buffer receives the output clock signal to generate the feedback signal, and buffer further using a slew rate control signal to control a slew rate of the feedback signal.

Sub-sampling phase-locked loop

A clock and data recovery device and a jitter tolerance enhancement method thereof are provided. The clock and data recovery device includes a clock and data recovery circuit and a jitter tolerance enhancement circuit. A data input terminal of the clock and data recovery circuit is suitable for receiving a data signal. The clock and data recovery circuit recovers the data signal to a clock. The jitter tolerance enhancement circuit is coupled to the data input terminal of the clock and data recovery circuit to receive the data signal. The jitter tolerance enhancement circuit detects a correlation between the data signal and the clock and correspondingly adjusts a loop gain of the clock and data recovery circuit according to the correlation.

Clock and data recovery device and jitter tolerance enhancement method thereof

A reference voltage generator includes a detecting voltage provider, a comparator, and a core circuit. The detecting voltage provider provides a detecting voltage with a first voltage level corresponding to a voltage coefficient. The comparator compares the first voltage level of the detecting voltage with a plurality of sampled amplitudes of an input signal to respectively generate a plurality of comparison results. The core circuit is used to: collect a plurality of first comparison results associated with a current received bit of a preset value from the comparison results; take the voltage coefficient as a first boundary voltage coefficient in response to the first comparison results satisfying a first condition; take the voltage coefficient as a second boundary voltage coefficient in response to the first comparison results satisfying a second condition. The reference circuit generates a reference voltage according to the first and second boundary voltage coefficients.

Reference voltage generator

A dynamic amplifier includes a first output capacitor, a first switch, a current source, a second switch, a voltage detector, a third switch and a level shifter. The first switch is coupled between a first terminal of the first output capacitor and a voltage detection node. The second switch is coupled to the current source and the voltage detection node. The voltage detector is coupled to the voltage detection node and the first switch. The third switch is coupled between the voltage detection node and a power source. The level shifter is coupled to a second terminal of the first output capacitor.

Dynamic amplifier and related gain boosting method

A clock and data recovery circuit with jitter tolerance enhancement is provided. The CDR circuit includes: a bang-bang phase detector, a digital filter, a digitally controlled oscillator, and an adaptive loop gain control circuit. The CDR circuit detects a loop bandwidth variation and adjusts the loop bandwidth of CDR circuit by adjusting proportional path and integral path gain factors of the digital filter of the CDR circuit. The loop gain controller uses two methods to adjust the loop gain in CDR circuit: bang-bang adjusting method and linear adjusting method.

Clock and data recovery circuit with jitter tolerance enhancement

A differential signal correction circuit is disclosed. The differential signal correction circuit may comprise a first single-ended-to-differential converter and a second single-ended-to-differential converter. Each one of the two converters may comprise an input port and two output ports. The converters may be configured to perform a first phase correction for a pair of differential signals and output a first output signal and a second output signal. The first output signal is fed back to the first converter through one of the output ports of the first converter, and the second output signal is fed back to the second converter through one of the output ports of the second converter so as to perform phase correction and amplitude correction for the first output signal and the second output signal.

Differential signal correction circuit

One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulse) signal, a voltage controlled oscillator positive differential (VCOP) signal, and a voltage controlled oscillator negative differential (VCON) signal are received. An up signal and a down signal for a first charge pump (CP) and an up signal and a down signal for a second CP are generated based on the pulsesignal, the VCOP signal, and the VCON signal. For example, CP signals are generated to control the first CP and the second CP, respectively. In some embodiments, CP signals are generated such that the CPs facilitate adjustment of a zero crossing phase of the VCON and VCOP signals with respect to the pulsesignal. In this manner, a divider-less PLL is provided, thus mitigating PLL power consumption.

Divider-less phase locked loop (PLL)

The present invention discloses a noise filtering fractional-n frequency synthesizer and an operating method thereof. The noise filtering fractional-n frequency synthesizer comprises a filter, a frequency calibration loop, a phase calibration loop and a digitally controlled delay line. The filter receives a first frequency division signal and generates a filtered signal. The frequency calibration loop is coupled to the filter and generates a first control signal. The phase calibration loop is coupled to the filter and the frequency calibration loop, and generates a second control signal. The digitally controlled delay line is coupled to the phase calibration loop and receives the second control signal. Thus, quantization noise of the fractional-n frequency synthesizer can be reduced, and phase noise of the fractional-n frequency synthesizer can be improved. In addition, the system remains locked after the filter outputs the signal.

Noise filtering fractional-N frequency synthesizer and operating method thereof

The signal processing apparatus contains a first signal transforming circuit and a second signal transforming circuit. The first signal transforming circuit includes four first coupled lines and two second coupled lines, wherein two ends of each first coupled line are configured to carry a first pair of differential signals respectively, each second coupled line is magnetically coupled to two of the first coupled lines in parallel and comprises two signal ports, to which the two ends of each of the magnetically-coupled first coupled lines are placed symmetrically for transferring a second pair of differential signals. The second signal transforming circuit is configured to convert between the second pairs of differential signals at the signal ports and a third pair of differential signals at connecting ports of the second signal transforming circuit.

Signal processing apparatus

A limiting amplifier with an input stage with dc offset cancellation, identical gain stages, an output buffer and a feedback filter. The input stage receives a differential input signal and outputs a first intermediate differential signal. The gain stages are cascaded to amplify the first intermediate differential signal and generate a second intermediate differential signal, amplified by the output buffer to produce an output signal. The feedback filter provides a dc offset voltage of the output signal to the input stage for the dc offset cancellation. The input stage comprises a resistor network coupled between a pair of input nodes and a power line and comprising a common resistor, a pair of load resistors and a shunt resistor. The load resistors share a common terminal connected to the common resistor that is connected to the power line. The shunt resistor has two terminals respectively connected to the load resistors.

Limiting amplifiers

A time amplifier circuit has first and second inverters and first and second pull-down paths. Each inverter includes a first NMOS transistor and a first PMOS transistor. A source of the first NMOS transistor is coupled to a ground node directly or through a first additional NMOS transistor having a gate coupled to a respective input node. The first and second inverters are coupled to first and second input nodes and to first and second output nodes, respectively. The first pull-down path is from the first output node to the ground node and is enabled in response to the first input signal and the second output signal being high. The second pull-down path is from the second output node to ground and is enabled in response to the second input signal and the first output signal being high.

Method and apparatus for amplifying a time difference

A flip-flop circuit includes a D flip-flop and a leakage current suppression circuit. The D flip-flop receives an input signal and a clock signal, and outputs a voltage of the input signal at a rising or falling edge of the clock signal as an output signal. The leakage current suppression circuit detects an output error caused by the leakage current flowing through at least a floating node of the D flip-flop and compensates for the leakage current to correct the output error. The leakage current suppression circuit includes a detection circuit and a compensation circuit. The detection circuit receives the output signal and clock signal and detects whether the output error has occurred to generate a detection result. The compensation circuit compensates for the leakage current according to the detection result to correct the output error.

Flip-flop circuit and leakage current suppression circuit utilized in a flip-flop circuit

A clock and data recovery circuit is disclosed and comprises a gated voltage-controlled oscillator (GVCO), a PLL unit, a phase-controlled frequency divider, a multiplexer, a matching circuit and a double-edge-triggered D flip-flop (DDFF). The GVCO receives a data signal and a reference voltage to generate first and second clock signals. The PLL unit receives a reference clock signal and generates the reference voltage to adjust the first and second clock signals at the vicinity of the predetermined frequency. The phase-controlled frequency divider receives and divides the first clock signal by N to output a third clock signal. The multiplexer controlled by a selection signal receives and outputs the second or the third clock signal. The matching circuit receives the data signal and the selection signal to match the delays therebetween. The DDFF receives the output signals from the matching circuit and the multiplexer, and outputs a recovered data signal.

Multi-band burst-mode clock and data recovery circuit

Methods and apparatuses for time to digital conversion (TDC) are disclosed. A timing circuit comprises a TDC circuit, a calibration module, and a correction module. The TDC circuit is configured to provide a timing signal indicative of a timing difference between edges of a periodic reference clock signal and a variable feedback signal. The TDC circuit is also configured to provide a delay signal that is variably delayed relative to the reference clock signal. The calibration module is configured to provide a calibration signal to increase and decrease a total delay of the TDC circuit based on a time delay of the calibration signal plus a time delay of a correction signal. The correction module, which is configured to receive the timing signal and provide the correction signal, minimizes harmonic spurs in a frequency response of the timing signal by operating at a frequency of the reference clock signal.

Method and system for time to digital conversion with calibration and correction loops

An all-digital phase-locked loop (ADPLL) composed of digital circuits is provided. The ADPLL includes a phase-frequency detector (PFD), a control unit, a digital controlled oscillator (DCO), and a plurality of frequency dividers. A first frequency divider divides a frequency of a feedback signal CKby a natural number M to generate a first output signal CK/M. The PFD generates a decrement signal dn and an increment signal up, based on a phase difference and a frequency between a first reference clock signal CKand the first output signal CK/M. The DCO generates a clock signal CKbased on the digital control signals. A second frequency divider receives the digital control signals from the control unit and the CKfrom the DCO and divides the frequency of the CKby a bit number of the digital control signals to generate a feedback signal CKto the first frequency divider.

All digital phase-locked loop with widely locked frequency

Growing community of inventors

Taipei, Taiwan

Shen-Iuan Liu