Montage Technology (Shanghai) Co., Ltd.

Siemens Aktiengesellschaft

Infineon Technologies Ag

Nokia Corporation

Siemens Aktiengesellscaft

Montage Lz Technologies (Shanghai) Co., Ltd.

Shen Feng

Markus Scholz

Mingfu Shi

Edmund G&ouml;tz

Yu Chen

Jun Xu

Stefan Beyer

Gang Hu

Edmund Goetz

Xiaomin Si

Yuanfei Nie

Shunfang Wu

Meiwu Wu

Georg Lipperer

Yiu Leechung

Xinwu Cai

The present disclosure provides a reference clock signal injected phase locked loop circuit and an offset calibration method. The reference clock signal injected phase locked loop circuit includes a first pulse generator, a second pulse generator, a state machine, a pulse selection and amplification circuit, a voltage controlled delay line, a phase detector, and a filter, and forms an offset calibration loop, a phase locked loop, a voltage controlled oscillator loop, and an injection locked loop. The state machine disconnects the phase locked loop and the voltage controlled oscillator loop and enables the offset calibration loop to calibrate the phase detector; the state machine enables the phase locked loop and the voltage controlled oscillator loop and locks a signal of the second pulse generator; and the state machine enables the injection locked loop for injecting a first pulse signal of the first pulse generator.

Reference clock signal injected phase locked loop circuit and offset calibration method thereof

A quadrature phase signal generator comprises a relative delay unit, a phase detector, a first amplifier and a loop filter. The relative delay unit delays differential input signals and generates four delayed signals. The phase detector generates quadrature four phase output signals, a first voltage signal and a second voltage signal according to the four delayed signals. A difference of the first and the second voltage signals indicates a phase error of the quadrature four phase output signals. The first amplifier amplifies the voltage difference of the first and the second voltage signals. The loop filter filters the amplified voltage difference and generates a tuning voltage signal. The loop filter is further communicatively coupled to the relative delay unit. The relative delay unit adjusts a delay of the quadrature four phase delayed signals according to the tuning voltage signal.

Signal generator, electronic system comprising the signal generator and method of generating signals

A method and apparatus for measuring parameters of a receiver having a mixer for generating an I signal and a Q signal using an input signal, an I channel circuit for processing the I signal, and a Q channel circuit for processing the Q signal. The method includes feeding the receiver a first testing signal before the mixer. The method includes feeding the receiver a second testing signal on the I channel circuit. The method includes feeding the receiver a third testing signal on the Q channel circuit. The method includes measuring I/Q quadrature deviation and I/Q delay imbalance of the receiver using the first, the second, and the third testing signals. This separates the I/Q quadrature deviation and I/Q delay imbalance.

Method and apparatus for measuring and correcting receiver parameters

A signal processing method and system are provided. The method includes receiving an input signal within a first frequency range, the input signal including a desired signal and an interference signal. The method includes down-converting the input signal to a second frequency range, which is lower than the first frequency range, using an offset local oscillator signal having a frequency substantially equal to the central frequency of the desired signal. The method includes separating the interference signal from the down-converted input signal. The method includes up-converting the separated interference signal to the first frequency range. The method includes subtracting the up-converted interference signal from the input signal at the first frequency range to obtain an interference removed signal. The method includes down-converting the interference removed signal to a third frequency range, which is lower than the first frequency range, using a local oscillator signal, for demodulating. The frequency of the offset local oscillator signal is different from the frequency of the local oscillator signal.

Method and apparatus for processing signal

A direct conversion receiver comprises a low noise amplifier, a bandpass filter, a mixer circuit and a baseband processing assembly. The low noise amplifier is capable of receiving communication signals from an antenna and, in turn, the bandpass filter is capable of filtering the received signals to a bandpass including a reception frequency band. The mixer circuit is electrically connected to an output of the bandpass filter, and can demodulate the received signals into differential signals in two channels. The baseband processing assembly is electrically connected to the mixer circuit opposite said bandpass filter. In this regard, the baseband processing assembly can process the demodulated differential signals in at least one of the channels. And to compensate DC offset from the demodulated differential signals, for each channel the baseband processing assembly includes a pair of dynamic offset compensation elements and a static offset compensation element.

Offset compensation in a direct-conversion receiver

A phase-locked loop circuit is described and has a digital circuit section and an analog circuit section that are fed with different supply voltages. Control signals generated by the digital circuit section are conducted to the analog circuit section via level converters and therefore can control functions in the analog circuit section.

Electronic circuit, particularly for a mobile transceiver

A frequency synthesizer for a radio terminal with which a dual-band and/or dual-mode switchover is possible in a simple manner. The frequency synthesizer has a double phase-locked loop with a high-frequency portion and an intermediate-frequency portion, each with one divider and one counter in a feedback branch. There is at least one memory for holding a plurality of divider values for the counter in the intermediate-frequency portion. The counter in the high-frequency portion is coupled to the memory in such a way that when a new divider value is written into the counter of the high-frequency portion, an associated divider value from the memory is written into the counter of the intermediate-frequency portion. In this way, the frequency generated by the intermediate-frequency divider is adapted to the frequency generated in the high-frequency portion in such a way that the requisite operating frequencies of each active mobile radio system are set automatically. In the same way, the dual-mode switchover can be carried out by coupling a further memory with further divider values for the counter of the high-frequency portion.

Frequency synthesizer with a phase-locked loop for receiving and processing signals in different frequency bands

In a PLL circuit, the precharging function necessary for setting a required initial state of a VCO is achieved by an additional precharge pump inserted in parallel with the charge pump, or alternatively by multiplexers and inverters implemented directly with the charge pump. The precharging function being controlled in both cases by two control signals. PLL circuits according to the invention are applied, in particular, in integrated circuits of mobile transceivers, for example for GSM, PCN and PCS.

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Shen Feng