Signetics

North American Philips Corporation

North American Philips Corp, Signetics Division

Sheldon C Lim

Ting P Yen

Julie W Hellstrom

George W Conner

William T Stacy

Stanley C Chu

Saiyed A Raza

Kevin G Jew

Douglas F Ridley

The properties of a diffusion barrier material layer over a semiconductor substrate are enhanced in a simple and time-effective manner by immersing the substrate in an oxidizing liquid. For a titanium-tungsten barrier metal, a dip in nitric acid for 1-60 minutes provides the metal with an oxide layer of the right thickness of 10-20 .ANG..

Barrier layer enhancement in metallization scheme for semiconductor

The size of a fusible link (22 C.sub.F) created from part of a metal layer (22) is controlled by an oxidation performed in a deposition chamber that is also used for depositing a dielectric layer (30) over the fuse structure. The metal layer serves as a diffusion barrier between semiconductor material (14 and 16) and another metal layer (24).

Programmable semiconductor integrated circuits having fusible links

The present invention provides a method of forming fuse ribbons between conductive layers on a semiconductor device. The formation of these fuse ribbons may be at different levels of multiple level integrated circuits. The fuse ribbons are formed in a more precise manner than can be obtained conventionally. Resistance control can be easily achieved and significant decreases in dimensions and the use of less fuse material can be achieved.

Method of manufacturing fusible links in semiconductor devices

The size of a fusible link (22C.sub.F) created from part of a metal layer (22) is controlled by an oxidation performed in a deposition chamber that is also used for depositing a dielectric layer (30) over the fuse structure. The metal layer serves as a diffusion barrier between semiconductor material (14 and 16) and another metal layer (24).

Fabrication method using oxidation to control size of fusible link

A technique for producing planarized semiconductor surfaces and for isolating semiconductor islands.

Planarization method and technique for isolating semiconductor islands

In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor is introduced into one of the islands to produce a region (48) of opposite type conductivity (P) that forms a PN junction with adjacent semiconductive material of the island. Ions are implanted to convert a surface layer (60) of the region into a highly resistive amorphous form which is irreversibly switchable to a low resistance state. A path of first type conductivity extending from the PN junction through another of the islands to its upper surface is created in the body to complete the basic cell.

Method of fabricating a programmable read-only memory cell incorporating

In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor impurity is introduced into one of the islands to produce a region (48) of opposite type conductivity (P) that forms a PN junction laterally bounded by the island's side boundaries. A highly resistive amorphous semiconductive layer (58) which is irreversibly switchable to a low resistive state is deposited above the region in such a manner as to be electrically coupled to the region. A path of first type conductivity extending from the PN junction through another of the islands to its upper surface is created in the body to complete the basic cell.

A film of titanitum-tungsten nitride is used to provide the dual function of a fuse link between a semiconductive device and an interconnect line in a memory array and of a barrier metal between another metal and a semiconductor region.

Growing community of inventors

Sunnyvale, CA, United States of America

Sheldon C Lim