Lsi Logic Corporation

National Semiconductor Corporation

Lsi Corporation

Fairchild Semiconductor Corporation

Sheldon Aronowitz

Vladimir Zubkov

James O Kimball

Courtney L Hart

Helmut Puchner

Nicholas K Eib

Richard D Schinella

Valeriy K Sukharev

Jon S Owyang

John Haywood

Abraham Fong Yee

James P Kimball

Grace S Sun

Yu-Lam Ho

Sung T Ahn

Laique Khan

Constantin Bulucea

Douglas Ticknor Grider

Gobi R Padmanabhan

David C Lee

Ravindra Manohar Kapre

Paul Rissman

Amolak R Ramde

Chi-Yi Kao

David Chan

George P Walker

Aldona M Butkus

Bhaskar V Gadepally

Court Skinner

Esin Dermirlioglu

Matthew S Buynoski

Nicholas F Pasch

Philippe Schoenborn

Robert J Strain

Mohammad R Mirabedini

Gary K Giust

Rosario J Consiglio

Norman E Abt

Esin Kutlu Demirlioglu

Shih-Fen Huang

Lindor Eric Henrickson

Farrokh Mohammadi

Yen-Hui Joseph Ku

Donald D Forsythe

Kranti V Anand, Deceased

Peter P Meng

Mohammed Mirabedini

Nicholas F Pasen

Ravindra A Kapre

A barrier layer for a semiconductor device is provided. The semiconductor device comprises a dielectric layer, an electrically conductive copper containing layer, and a barrier layer separating the dielectric layer from the copper containing layer. The barrier layer comprises a silicon oxide layer and a dopant, where the dopant is a divalent ion, which dopes the silicon oxide layer adjacent to the copper containing layer. A method of forming a barrier layer is provided. A silicon oxide layer with a surface is provided. The surface of the silicon oxide layer is doped with a divalent ion to form a barrier layer extending to the surface of the silicon oxide layer. An electrically conductive copper containing layer is formed on the surface of the barrier layer, where the barrier layer prevents diffusion of copper into the substrate.

Method for creating barriers for copper diffusion

Techniques for vaporizing and handling a vaporized metallic element or metallic element salt with a heated inert carrier gas for further processing. The vaporized metallic element or salt is carried by an inert carrier gas heated to the same temperature as the vaporizing temperature to a heated processing chamber. The metal or salt vapor may be ionized (and implanted) or deposited on substrates. Apparatus for accomplishing these techniques, which include carrier gas heating chambers and heated processing chambers are also provided.

Method of treating metal and metal salts to enable thin layer deposition in semiconductor processing

Method of vaporizing and ionizing metals for use in semiconductor processing

An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric region formed over a channel region. A doped region is formed between a top portion and a bottom portion of the dielectric region. This doped region includes a suitable electron affinity material. A gate electrode is connected with the top of the dielectric region. In some embodiments, suitable electron affinity materials are introduced into the doped region using implantation techniques. In another embodiment, the electron affinity material is introduced into the doped region using plasma treatment of the dielectric region and the redeposition of additional dielectric material on top of the dielectric region and doped region.

Method and apparatus for forming a memory structure having an electron affinity region

Vaporization and ionization of metals for use in semiconductor processing

A method of forming a layer over a substrate is provided. Generally, a layer of a first reactive species is deposited over the substrate. The layer of the first reactive species is reacted with a second reactive species to create a first product. Unreacted reactive species is preferentially desorbed leaving a layer of the first product.

Method for growing thin films

The invention provides a process for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes containing one or more organofluoro silanes having the formula SiRRRR, where: (a) Ris selected from H, a 3 to 10 carbon alkyl, and an alkoxy; (b) Rcontains at least one C atom bonded to at least one F atom, and no aliphatic C&#x2014;H bonds; and (c) Rand Rare selected from H, alkyl, alkoxy, a moiety containing at least one C atom bonded to at least one F atom, and ((L)Si(R)(R))(R); where n ranges from 1 to 10; L is O or CFR; each n Rand Ris selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom; Ris selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom; and each Ris selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom. Also provided is a low dielectric constant fluorine and carbon-doped silicon oxide dielectric material for use in an integrated circuit structure which contains: silicon atoms bonded to oxygen atoms; silicon atoms bonded to carbon atoms; and carbon atoms bonded to fluorine atoms; where the dielectric material also has a characteristic selected from: (a) the presence of at least one C&#x2014;C bond; (b) the presence of at least one carbon atom bonded to from 1 to 2 fluorine atoms; and (c) the presence of at least one silicon atom bonded to from 0 to 2 oxygen atoms.

Low dielectric constant fluorine and carbon-containing silicon oxide dielectric material characterized by improved resistance to oxidation

An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric stack formed over a channel region of a semiconductor substrate. The dielectric stack includes a layer of electron trapping material that operates as a charge storage center for memory devices. A gate electrode is connected with the top of the dielectric stack. In various embodiments the electron trapping material forms a greater or lesser portion of the dielectric stack. The invention includes a method embodiment for forming such a memory device.

Memory device having an electron trapping layer in a high-K dielectric gate stack

A calcium doped polysilicon gate electrodes for PMOS containing semiconductor devices. The calcium doped PMOS gate electrodes reduce migration of the boron dopant out of the gate electrode, through the gate dielectric and into the substrate thereby reducing the boron penetration problem increasingly encountered with smaller device size regimes and their thinner gate dielectrics. Calcium doping of the gate electrode may be achieved by a variety of techniques. It is further believed that the calcium doping may improve the boron dopant activation in the gate electrode, thereby further improving performance.

Calcium doped polysilicon gate electrodes

A new relatively high-k gate dielectric gate material comprising calcium oxide will reduce leakage from the silicon substrate to the polysilicon gate, prevent boron penetration in p-channel devices, and reduce electron trapping in the dielectric. The surface of a silicon wafer is saturated with hydroxyl groups. A calcium halide, preferably calcium bromide, is heated to a temperature sufficient to achieve atomic layer deposition, and is transported to the silicon wafer. The calcium halide reacts with the hydroxyl groups. Water is added to carry away the resultant hydrogen halide. Gaseous calcium and water are then added to form a calcium oxide gate dielectric, until the desired thickness has been achieved. In an alternative embodiment of the method, the calcium halide is transported to the silicon wafer to react with the hydroxyl groups, followed by transport of gaseous water to the silicon wafer. These two steps are repeated until the desired thickness has been achieved.

High-K dielectric gate material uniquely formed

A method of preparing a polysilicon gate to minimize gate depletion and dopant penetration and to increase conductivity is revealed. Several monolayers of atomic are condensed onto a gate dielectric. Polysilicon is deposited onto the calcium and patterned in a standard way. The exposed calcium is then removed by raising the temperature to approximately 600&#xb0; C. The calcium remaining between the gate dielectric and the polysilicon blocks channeling of dopant to minimize depletion and penetration, increase conductivity, and allow for longer and higher-temperature annealing.

Process to minimize polysilicon gate depletion and dopant penetration and to increase conductivity

The invention provides a process for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes that include one or more organofluoro silanes selected from: (a) an organofluoro silane containing two silicon atoms linked by one oxygen atom; (b) an organofluoro silane containing two silicon atoms linked by one or more carbon atoms, where the one or more carbon atoms each are bonded to one or more fluorine atoms, or to one or more organofluoro moieties, or to a combination thereof; and (c) an organofluoro silane containing a silicon atom bonded to an oxygen atom. The invention also provides a process for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes that include one or more organofluoro silanes characterized by the presence of Si&#x2014;O bonds.

Process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material

A method of forming a narrow isolation structure in a semiconducting substrate. The isolation structure is a trench that has a bottom and sidewalls, and that is to be filled with an isolating material. The isolating material has desired electrical properties and desired chemical properties, and is substantially reactively grown from the semiconducting substrate. A precursor material layer is formed on the bottom of the trench and on the sidewalls of the trench. The precursor material layer has electrical properties and chemical properties that are substantially similar to the desired electrical properties and the desired chemical properties of the isolating material. A substantial portion of the precursor material layer is removed from the bottom of the trench to expose the semiconducting substrate at the bottom of the trench, while leaving a substantial portion of the precursor material layer on the sidewalls of the trench. The isolating material is reactively grown in the trench, where the isolating material preferentially grows from the exposed semiconducting substrate at the bottom of the trench at a first rate. The precursor material layer at least partially inhibits formation of the isolating material from the semiconducting substrate at the sidewalls of the trench. The isolating material forms from the sidewalls of the trench at a second rate, where the first rate is substantially higher than the second rate. Thus, by forming a precursor layer that inhibits formation of the isolation material at the sidewalls of the trench, the isolation material preferentially grows from the bottom of the trench rather than expanding sideways from the sidewalls of the trench, which tends to widen the isolation structure. Because the precursor layer has properties that are substantially similar to those that are desired in the isolation material, the precursor layer remains at the sidewalls of the trench near the edge of the isolation structure. Therefore, the isolation structure functions as desired, but is narrower than it otherwise would be, if the precursor layer had not been formed.

Integrated circuit isolation system

A method of chemically altering a silicon surface and associated dielectric materials are disclosed.

Method of chemically altering a silicon surface and associated electrical devices

Growing community of inventors

San Jose, CA, United States of America

Sheldon Aronowitz