Eastman-kodak Company

Xerox Corporation

Mosaic Microsystems LLC

Eastman Kodak

Eastmak Kodak Company

Shelby Forrester Nelson

Carolyn Rae Ellinger

Lee William Tutt

David Howard Levy

Diane Carol Freeman

Deepak Shukla

Peter Jerome Cowdery-Corvan

Wendy G Ahearn

Alan D Raisanen

Jeffrey T Carey

Todd Mathew Spath

Kurt DeLance Sieber

Thomas D Pawlik

Ronald S Cok

Roger Stanley Kerr

Mitchell Stewart Burberry

Lyn Marie Irving

Christopher R Morton

Andrew D Thompson

Jeffrey Todd Carey

An inorganic substrate with an improved via shape and methods for facilitating formation of such improved via shape are disclosed. A double-sided opening process may be applied to an inorganic substrate to form openings at the ends of a damage track previously formed in the inorganic substrate. One side of the inorganic substrate may then be sealed, such as by being temporarily bonded to a carrier or blocking substrate, so that a single-sided opening process may be applied to the other unsealed or unblocked surface of the inorganic substrate. The single-sided opening process may enlarge at least one of the openings formed by the double-sided opening process and may enlarge a channel between the openings to form a via having an advantageous shape.

Facilitating formation of a via in a substrate

Processed inorganic wafers and processing a wafer stack including an abrasive process are disclosed. A wafer stack may be formed at least by performing a temporary bonding process to temporarily bond at least a first inorganic wafer to a first surface of a handle wafer. The handle wafer may include at least one inorganic wafer, and the temporary bonding process may include formation of an adhesion layer between the first inorganic wafer and the first surface of the handle wafer. The adhesion layer may include a vacuum deposited carbonaceous film with a thickness between 1 nm and 100 nm, inclusive. An abrasive process may be applied to at least part of the wafer stack, and the abrasive process may reduce a thickness of the first inorganic wafer of the wafer stack. The first inorganic wafer may be debonded from the handle wafer after applying the abrasive process.

Processed inorganic wafer and processing wafer stack with abrasive process

A modular thin film deposition system, includes a machine base, a deposition head for depositing a thin film of material onto a process surface of a substrate, a motion actuator including a fixed portion and a moveable portion, and one or more interchangeable substrate positioner modules adapted to mount on the moveable portion of the motion actuator. The interchangeable substrate positioner modules include kinematic mounting features that engage with corresponding kinematic mounting features on the moveable portion of the motion actuator. The motion actuator moves the interchangeable substrate positioner in a motion direction, thereby moving the substrate in an in-track direction in a plane parallel to the output face of the deposition head during deposition of the thin film of material onto the process surface of the substrate.

Modular thin film deposition system

A material deposition system for depositing a material on a surface of a substrate includes a deposition head having an output face configured to simultaneously supply a plurality of gaseous materials in a sequence of gas zones. The gas zones include a deposition zone located between first and second inert zones. The deposition zone includes a first reactant zone adjacent to the first inert zone, a last reactant zone adjacent to the second inert zone, and one or more purge gas zones. A motion actuator moves a substrate over the output face with a repeating motion profile that prevents a region of active deposition on the substrate from being exposed to the external environment prior to having achieved a final material deposition amount. The repeating motion profile include a forward motion portion and a backward motion portion which is less than the forward distance by an ooch distance.

Deposition system with repeating motion profile

An electronic element includes a substrate, and a vertical-support-element located on the substrate, the vertical-support-element extending away from the substrate and having a perimeter over the substrate, wherein the vertical-support-element has a reentrant profile around at least a portion of the perimeter. Three or more vertical transistors are positioned around the perimeter of the vertical-support-element, each of the transistors having a semiconductor channel being located in a corresponding region of the reentrant profile.

Multiple TFTs on common vertical support element

A method of forming a thin-film transistor includes providing a substrate having a top surface and a recess in the top surface. An electrically conductive gate is provided within the recess. A conformal insulating material layer and a conformal semiconductor material layer are formed in the recess, with the semiconductor material layer extending over the top surface of the substrate outside of the recess. Source and drain electrodes are formed by adding a deposition inhibitor material on a portion of the substrate including within the recess; and depositing a thin-film of electrically conductive material, wherein the deposition inhibitor material inhibits the deposition of the electrically conductive material such that the electrically conductive material is patterned by the deposition inhibitor material during deposition, wherein the patterned electrically conductive material provides the source electrode on a first side of the recess and the drain electrode on a second side of the recess.

Method for forming a thin-film transistor

An electronic device includes a vertical-support-element with first and second edges having first and second reentrant profiles, respectively. The first reentrant profile includes first conformal semiconductor and dielectric layers, and a conformal conductive top-gate. A first electrode contacts a first portion of the first conformal semiconductor layer over the top of the vertical-support-element. A second electrode, adjacent to the first edge, contacts a second portion of the first conformal semiconductor layer not over the vertical-support-element. The second reentrant profile includes a conformal conductive bottom-gate, and second conformal dielectric and semiconductor layers. A third electrode, adjacent to the second edge, contacts the second semiconductor layer not over the vertical-support-element. A fourth electrode, over the vertical-support-element, contacts the second semiconductor layer. The first and second electrodes define a first semiconductor channel of a top-gate transistor, the third and fourth electrodes define a second semiconductor channel of a bottom-gate transistor.

Bottom-gate and top-gate VTFTs on common structure

A transistor includes a substrate and an electrically conductive gate over the substrate. The gate has a gate length. A source electrode and a drain electrode are over the substrate, and are separated by a gap defining a channel region. The channel region has a channel length that is less than the gate length. A semiconductor layer is in contact with the source electrode and drain electrode. A dielectric stack is in contact with the gate, and has first, second, and third regions. The first region is in contact with the semiconductor layer in the channel region, and has a first thickness. The second region is adjacent to the first region that has the first thickness. The third region is adjacent to the second region, and has a thickness that is greater than the first thickness.

TFT substrate with variable dielectric thickness

An enhancement-depletion circuit element includes a depletion-mode load transistor and an enhancement-mode drive transistor formed from the common elements of: a first patterned conductive layer including a load gate electrode and a drive gate electrode; a patterned inorganic dielectric stack including a load gate dielectric and a drive gate dielectric; a patterned inorganic semiconductor layer including a load semiconductor region and a drive semiconductor region; a second patterned conductive layer including a load source, a load drain, a drive source and a drive drain; and a patterned differential passivation structure having a patterned polymer dielectric layer and a patterned conformal inorganic dielectric layer. The depletion-mode load transistor has a load back-channel in contact with the patterned conformal inorganic dielectric layer. The enhancement-mode drive transistor has a drive back-channel in contact with the patterned polymer dielectric layer.

Enhancement-depletion mode circuit element with differential passivation

An electronic device includes a vertical-support-element on a substrate. The vertical-support-element extends away from the substrate and includes a first edge having a first reentrant profile. A conformal semiconductor layer is in contact with the vertical-support-element in the reentrant profile. A first electrode is in contact with a first portion of the semiconductor layer and is located over a top of the vertical-support-element. A second electrode is in contact with a second portion of the semiconductor layer and is located over the substrate and not over the vertical-support-element. The second electrode is adjacent to the first edge of the vertical-support-element. A conformal dielectric layer is on the conformal semiconductor layer in the reentrant profile. A conformal conductive gate is on the conformal dielectric layer in the first reentrant profile. The first electrode and the second electrode define a semiconductor channel of a transistor.

VTFT with a top-gate structure

A transistor includes a substrate and a polymer layer that is in contact with the substrate. The polymer layer has a first pattern defining a first area. There is an inorganic semiconductor layer over and in contact with the polymer layer that has a second pattern defining a second area. The first area is located within the second area. There is a source electrode in contact with a first portion of the semiconductor layer and a drain electrode in contact with a second portion of the semiconductor layer, and the source electrode and the drain electrode separated by a gap. A gate insulating layer is in contact with the inorganic semiconductor layer in the gap. There is a gate in contact with the gate insulating layer over the gap.

Top gate TFT with polymer interface control layer

An enhancement-mode inverter includes a load transistor and a drive transistor. The load transistor has a bottom gate architecture with a first source, a first drain, a load channel region, a first semiconductor layer, and a first gate electrode. A load gate dielectric is in the load channel region, and has a load dielectric thickness. The drive transistor has a bottom gate architecture with a second source, a second drain, a drive channel region, a second semiconductor layer, and a second gate electrode. A drive gate dielectric is in the drive channel region, and has a drive dielectric thickness less than the load dielectric thickness. The first source is electrically connected to the second drain and the first gate is electrically connected to the first drain. The load gate dielectric and the drive gate dielectric are part of a common shared dielectric stack.

Enhancement mode inverter with variable thickness dielectric stack

An enhancement-depletion-mode inverter includes a load transistor and a drive transistor. The load transistor has a top gate architecture with a first source, a first drain, a load channel region, a first semiconductor layer, and a first gate electrode. A load gate dielectric is in the load channel region, and has a load dielectric thickness. The load transistor is configured to operate in a depletion mode. The drive transistor has a bottom gate architecture with a second source, a second drain, a drive channel region, a second semiconductor layer, and a second gate electrode. A drive gate dielectric is in the drive channel region, and has a drive dielectric thickness that is different from the load dielectric thickness. The drive transistor is configured to operate in a normal mode or an enhancement mode. The first source is electrically connected to the second drain and the first gate.

Enhancement-depletion mode inverter with two transistor architectures

A transistor includes a substrate, an electrically conductive material layer, and an electrically insulating material layer. At least a portion of one or more of the substrate, the electrically conductive material layer, and the electrically insulating material layer define a reentrant profile.

Transistor including reentrant profile

A method of producing a patterned polymeric insulator includes providing a substrate. A patterned polymeric inhibitor is provided on the substrate. An inorganic thin film is deposited using an atomic layer deposition process on the substrate in an area where the patterned polymeric inhibitor is absent. A material layer is deposited over the inorganic thin film and the patterned polymeric inhibitor.

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Pittsford, NY, United States of America

Shelby Forrester Nelson