Intel Corporation

Micron Technology Incorporated

Shekoufeh Qawami

Rajesh Sundaram

Subramaniam M Maiyuran

Doyle W Rivers

Salvador Palanca

Blaise B Fanning

Stephen Anthony Fischer

David Zimmerman

Prashant S Damle

Julie M Walker

Sean Stephen Eilert

Derchang Kau

Frank T Hady

Raymond Scott Tetrick

Rita H Wouhaybi

Kiran Pangal

Hassnaa Moustafa

Robert W Faber

Rodney R Rozman

Jared E Hulbert

Chaitanya Sreerama

Nadine L Dabby

Raymond W Zeng

Owen W Jungroth

Daniel Chu

Michael J Allen

Kooi Chi Ooi

Niranjan L Cooray

Albert Fazio

Casey Baron

Chaitanya S Rajguru

Angad Narang

Naissa Conde

Mengjie Yu

Amirali Khatib Zadeh

Pavel Poliakov

Andrey Kudryavtsev

Van H Le

Glenn J Hinton

Nageen Himayat

Linda L Hurd

Lance W Dover

Sanjay S Talreja

Geoffrey A Gould

Benjamin Graniello

Gayathri Jeganmohan

Ankitha Chandran

Philip Hillier

Joel T Jorgensen

Monte Klinkenborg

Michael Allen

Techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessible by a host device during a normal mode of operation. Post-manufacturing updates to trim parameters by the host device may be feasible by creating registers located within the memory device that are accessible to the host device to provide information regarding trim parameter setting updates. The memory device may read the information from the registers accessible to the host device to update trim parameters stored in the register inaccessible by the host device. In this manner, the host device may not have a direct access to the trim parameters but still be able to provide an update to the trim parameters by updating an entry of the registers accessible by the host device.

Techniques to update a trim parameter in non-volatile memory

Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may include a plurality of local controllers that each independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands. The apparatus may include a controller to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands. The controller may be provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.

Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory

Methods, apparatus, systems and articles of manufacture are disclosed to add common sense to a human machine interface. Disclosed examples include a human machine interface system that having an actuator to cause artificial intelligence to execute in a virtual execution environment to generate a virtual response to a user input. The system also includes a virtual consequence evaluator to evaluate a virtual consequence that follows from the virtual response, the virtual consequence generated by executing a model of human interactions, and an output device controller to cause an output device to perform a non-virtual response to the user input when the virtual consequence evaluator evaluates the virtual consequence as positive.

Methods and apparatus to add common sense reasoning to artificial intelligence in the context of human machine interfaces

Methods, apparatus, systems and articles of manufacture are disclosed to improve boundary excursion detection. An example apparatus to improve boundary excursion detection includes a metadata extractor to parse a first control stream to extract embedded metadata, a metadata label resolver to classify a boundary term of the extracted embedded metadata, a candidate stream selector to identify candidate second control streams that include a boundary term that matches the classified boundary term of the first control stream, and a boundary vector calculator to improve boundary excursion detection by calculating a boundary vector factor based on respective ones of the candidate second control streams that include the classified boundary term.

Methods, systems, articles of manufacture and apparatus to improve boundary excursion detection

Apparatuses and methods for evaluating the risk factors of a proposed vehicle maneuver using remote data are disclosed. In embodiments, a computer-assisted/autonomous driving vehicle communicates with one or more remote data sources to obtain remote sensor data, and process such remote sensor data to determine the risk of a proposed vehicle maneuver. A remote data source may be authenticated and validated, such as by correlation with other remote data sources and/or local sensor data. Correlation may include performing object recognition upon the remote data sources and local sensor data. Risk evaluation is performed on the validated data, and the results of the risk evaluation presented to a vehicle operator or to an autonomous vehicle navigation system.

Evaluating risk factors of proposed vehicle maneuvers using external and internal data

Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. Such a next partition command may use fewer clock cycles than a command that includes a complete instruction and memory location information.

Memory access techniques in memory devices with multiple partitions

Subject matter disclosed herein relates to management of a memory device.

Phase change memory in a dual inline memory module

Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands. The controller may be further configured to provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.

Methods and apparatus to train interdependent autonomous machines are disclosed. An example method includes performing an action of a first sub-task of a collaborative task with a first collaborative robot in a robotic cell while a second collaborative robot operates in the robotic cell according to a first recorded action of the second collaborative robot, the first recorded action of the second collaborative robot recorded while a second robot controller associated with the second collaborative robot is trained to control the second collaborative robot to perform a second sub-task of the collaborative task, and training a first robot controller associated with the first collaborative robot based at least on a sensing of an interaction of the first collaborative robot with the second collaborative robot while the action of the first sub-task is performed by the first collaborative robot and the second collaborative robot operates according to the first recorded action.

Methods and apparatus to train interdependent autonomous machines

A memory device has multiple nonvolatile (NV) memory arrays that collectively store a block of data, with each array to store a portion of the data block. A selected NV memory array stores a write count for the block of data. In response to a write command, the NV memory arrays that store data perform an internal pre-write read. The selected NV memory array that stores the write count will perform a pre-write read of the write count, increment the write count internally to the selected NV memory array, and write the incremented write count back to the selected NV memory array.

Auto-increment write count for nonvolatile memory

Techniques to update a trim parameter in nonvolatile memory

A memory system includes a nonvolatile (NV) memory device with asymmetry between intrinsic read operation delay and intrinsic write operation delay. The system can select to perform memory access operations with the NV memory device with the asymmetry, in which case write operations have a lower delay than read operations. The system can alternatively select to perform memory access operations with the NV memory device where a configured write operation delay that matches the read operation delay.

Configurable write command delay in nonvolatile memory

According to one embodiment of the present invention, an apparatus is disclosed. The apparatus includes a memory array having a plurality of memory cells. The apparatus further includes memory access circuits coupled to the memory array and configured to perform write operations responsive to control signals. The apparatus further includes control logic coupled to the memory access circuits and configured to apply a set of write parameters based, at least in part, on a number of write operations performed by the memory access circuits and further configured to provide control signals to the memory access circuits to perform write operations on the plurality of memory cells according to the set of write parameters.

Apparatuses and methods for adjusting write parameters based on a write count

Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.

Scalable bandwidth non-volatile memory

Growing community of inventors

El Dorado Hills, CA, United States of America

Shekoufeh Qawami