Advanced Micro Devices Corporation

Other

Shekhar Pramanick

Takeshi Nogami

Ming-Ren Lin

Dirk Dewar Brown

Qi Xiang

Minh Van Ngo

John A Iacoponi

Che-Hoo Ng

Bin Yu

Sergey D Lopatin

Bhanwar Singh

Zoran Krivokapic

Guarionex Morales

David S Bang

Paul Raymond Besser

Lu You

Scott D Luning

Witold P Maszara

Srinath Krishnan

Kai Yang

Jonathon Fewkes

Subhash Gupta

Christy Mei-Chu Woo

Richard J Huang

Suzette Keefe Pangrle

Deepak K Nayak

Emi Ishida

Khanh Q Tran

Akif Sultan

Susan H Chen

Geoffrey Choh-Fei Yeap

John T Yue

Sunny Cherian

Subash Gupta

Igor C Ivanov

A self-aligned semiconductor interconnect barrier between channels and vias is provided which is self-aligned and made of a metallic barrier material. A channel is conventionally formed in the semiconductor dielectric, lined with a first metallic barrier material, and filled with a conductive material. A recess is etched to a predetermined depth into the conductive material, and the second metallic barrier material is deposited and removed outside the channel. This leaves the conductive material totally enclosed in metallic barrier material. The metallic barrier material is selected from metals such as tantalum, titanium, tungsten, compounds thereof, alloys thereof, and combinations thereof.

Self-aligned semiconductor interconnect barrier and manufacturing method therefor

A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field defect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

Transistor with local insulator structure

The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member: (a) under plasma conditions with ammonia and silane or dichlorosilane to form a copper silicide layer thereon; or (b) with an ammonia plasma followed by reaction with silane or dichlorosilane to form a copper silicide layer thereon. The diffusion barrier layer is then deposited on the copper silicide layer. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, then treating the exposed surface of the Cu/Cu alloy interconnect to form the copper silicide layer thereon, and depositing a silicon nitride diffusion barrier layer on the copper silicide layer.

Method of forming reliable capped copper interconnects

A semiconductor device includes a T-shaped gate electrode. The T-shaped electrode may have a metal upper layer and a semiconductor lower layer with a diffusion barrier therebetween. The metal upper layer may be used as a gate mask to control implantation of ions in a semiconductor substrate. Gate metal-semiconductor portions may be electrically coupled to both the metal upper portion and the semiconductor lower portion thereby to reduce electrical resistance in the T-shaped electrode. A method of forming source and drain regions in the semiconductor device includes using the T-shaped gate electrode as an implant mask.

T-shaped gate device and method for making

The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member: (a) under plasma conditions with ammonia and silane or dichlorosilane to form a copper silicide layer thereon; or (b) with an ammonia plasma followed by reaction with silane or dichlorosilane to form a copper silicide layer thereon. The diffusion barrier layer is then deposited on the copper suicide layer. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, then treating the exposed surface of the Cu/Cu alloy interconnect to form the copper silicide layer thereon, and depositing a silicon nitride diffusion barrier layer on the copper silicide layer.

A method of manufacturing a semiconductor device includes: providing a semiconductor with a dielectric layer formed thereon; forming an opening in said dielectric layer, said opening defined by walls of said dielectric layer and exposes a portion of said semiconductor, forming a conductive layer in said opening; removing said conductive layer to said dielectric layer; and forming a barrier layer over said conductive layer and said dielectric layer, said barrier layer made of a compound of silicon nitride with a third material compounded therein wherein said third material is modulated in amount through said layer of silicon nitride.

Manufacturing method for semiconductor interconnect barrier of boron silicon nitride

A method for eliminating copper atomic residue from the channel oxide layer on semiconductors after chemical-mechanical polishing is provided. After chemical-mechanical polishing, the silicon oxide is plasma etched to remove its surface and any residue. After plasma etching, an etch stop layer of silicon nitride is deposited by chemical-vapor deposition. Both the plasma etch of the silicon dioxide and the chemical-vapor deposition of the silicon nitride can be performed in the same vacuum chamber in the same semiconductor processing tool with only a change of the gas mixture.

Prevention of inter-channel current leakage in semiconductors

A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

Method of manufacturing a transistor with local insulator structure

A semiconductor interconnect barrier between channels and vias is provided which made of a metallic barrier material. In one embodiment, a first channel is conventionally formed in the semiconductor dielectric, lined with a first barrier material, and filled with a first conductive material. A layer of titanium nitride is formed atop the first channel of the first conductive material. Thereafter, a second channel is conventional formed in a second channel oxide, lined with a second barrier material. The second barrier material is selected from metals such as tantalum, titanium, tungsten, compounds thereof, alloys thereof, and combinations thereof. The combination of the titanium nitride layer and the second barrier material provide a superior barrier for conductive material layers, such as, copper/copper layers, and copper/aluminum layers.

Semiconductor interconnect barrier and manufacturing method thereof

A test structure used to measure metal bottom coverage in semiconductor integrated circuits. The metal is deposited in etched trenches, vias and/or contacts created during the integrated circuit manufacturing process. A predetermined pattern of probe contacts are disposed about the semiconductor wafer. Metal deposited in the etched areas is heated to partially react with the underlying and surrounding undoped material. The remaining unreacted metal layer is then removed, and an electrical current is applied to the probe contacts. The resistance of the reacted portion of metal and undoped material is measured to determine metal bottom coverage. Some undoped material may also be removed to measure metal sidewall coverage. The predetermined pattern of probe contacts is preferably arranged in a Kelvin or Vander Paaw structure.

Test structure used to measure metal bottom coverage in trenches and vias/contacts and method for creating the test structure

A self-aligned SOI device with body contact and silicide gate. The SOI device is formed using an ordinary substrate such as silicon. A silicide gate is self-aligned and formed from re-crystallization of nickel and amorphous silicon. The self-aligned silicide gate includes gate contact areas, and is self-aligned with respect to the gate opening, the source and drain regions and a nitride isolation layer. Nickel spacers deposited adjacent the isolation layer, and amorphous silicon deposited between the nickel spacers, form the self-aligned silicide gate through a silicidation process.

Self-aligned SOI device with body contact and NiSi2 gate

Low resistance contacts are formed on source/drain regions and gate electrodes by selectively depositing a reaction barrier layer and selectively depositing a metal layer on the reaction barrier layer. Embodiments include selectively depositing an alloy of cobalt and tungsten which functions as a reaction barrier layer preventing silicidation of a layer of nickel or cobalt selectively deposited thereon. Embodiments also include tailoring the composition of the cobalt tungsten alloy so that a thin silicide layer is formed thereunder for reduced contact resistance.

Low resistance composite contact structure utilizing a reaction barrier layer under a metal layer

A semiconductor barrier layer and manufacturing method therefor for copper interconnects which is a tantalum-titanium, tantalum-titanium nitride, tantalum-titanium sandwich. The tantalum in the tantalum-titanium alloy bonds strongly with the semiconductor dielectric, the tantalum-titanium nitride acts as the barrier to prevent diffusion of copper, and the titanium bonds strongly with the copper.

Alloy barrier layers for semiconductors

A shallow abrupt junction is formed in a single crystal substrate, for example, to form a pn junction in a diode or a source drain extension in a transistor. An amorphous layer is formed at the surface of the substrate by implanting an electrically inactive ion, such as germanium or silicon, into the substrate. The amorphous/crystalline interface between the amorphous layer and the base crystal substrate is located at the depth of the desired junction. A dopant species, such as boron, phosphorus or arsenic is implanted into the substrate so that peak concentration of the dopant is at least partially within the amorphous layer. The amorphous layer can be formed either before or after the implanting of the dopant species. A low temperature anneal is used to recrystallize the amorphous layer through solid phase epitaxy, which also activates the dopant within the amorphous layer. The dopant located beneath the original amorphous/crystalline interface remains inactive. Thus, an abrupt junction is formed at the depth of the original amorphous/crystalline interface. Formation of such a shallow abrupt junction is useful in devices such as diodes and transistors, including bipolar, MOSFET and CMOS, and may be used to form source drain extensions and halo regions. Subsequent processing of the substrate has a thermal budget that is approximately equal to or less than the temperature used for the low temperature anneal.

Formation of low thermal budget shallow abrupt junctions for semiconductor devices

The invention provides a system and a method for densifying a surface of a porous film. By reducing the porosity of a film, the method yields a densified film that is more impenetrable to subsequent liquid processes. The method comprises the steps of providing a film having an exposed surface. The film can be supported by a semiconductor substrate. When the film is moved to a processing position, a focused source of radiation is created by a beam source. The exposed surface of the film is then irradiated by the beam source at the processing position until a predetermined dielectric constant is achieved. The film or beam source may be rotated, inclined, and/or moved between a variety of positions to ensure that the exposed surface of the film is irradiated evenly.

Growing community of inventors

Fremont, CA, United States of America

Shekhar Pramanick