Xilinx, Inc.

Shekhar Bapat

Steven P Young

Kamal Chaudhary

Trevor J Bauer

Sridhar Krishnamurthy

Roman Iwanczuk

Bernard J New

Robert W Wells

Shahin Toutounchi

Robert D Patrie

Andrew W Lai

Nicolas J Camilleri

Tassanee Payakapan

Philip D Costello

Lawrence C Hung

Mohit Kumar Jain

Matthieu P H Cossoul

Steven M Trimberger

A method of testing a programmable device begins by programming at least a portion of the programmable device in accordance with at least a portion of an application to produce a programmed circuit, wherein the programmed circuit includes an input sequential element and an output sequential element. The method continues by providing a test input to the programmed circuit. The method continues by triggering the input sequential element to temporarily store the test input based on a first edge of the test clock. The method continues by triggering the output sequential element to temporarily store a test output of the programmed circuit based on a second edge of the test clock. The method continues by capturing the test output of the programmed circuit in accordance with the second edge of the test clock.

Testing of a programmable device

Methods of testing a user design implemented in a programmable integrated circuit (IC). The programmable IC is programmed with a first test design that includes the user design and a first test circuit, and a first test pattern is run. The programmable IC is then programmed with a second test design that includes the user design and a second test circuit, and a second test pattern is run. If one of the test patterns fails and the other passes, the programmable IC passes the test sequence. Because one of the test patterns passed, the error in the other test pattern must have occurred in the test circuit, which is not necessary for the functioning of the user design in the programmable IC. Thus, the success of one test pattern shows that the flawed resource is not included in the portion of the programmable IC utilized for implementing the user design.

Methods of testing a user design in a programmable integrated circuit

Method and apparatus for generating expected value data for testing a circuit configured in a programmable logic device (PLD). A simulation model is generated from a circuit representation for the circuit. Nodes in the simulation model configured for readback capture are automatically identified. The circuit representation is simulated as defined by the simulation model. Expected value data is recorded during the simulation in response to the identified nodes. A method and apparatus for testing a circuit configured in a PLD is also described. Expected value data for components of a circuit representation for the circuit is automatically generated using a modeling system, where the components are configured for readback capture. A test stimulus is applied to the circuit and state data is captured. The captured state data is compared with the expected value data.

Method and apparatus for automated generation of expected value data for circuit designs

A method of employing a plurality of integrated circuits in a multi-chip module is described. The method comprises steps of identifying a defective programmable logic device implemented on a first die; identifying a functional programmable logic device implemented on a second die; and coupling the defective programmable logic device and the functional programmable logic device. According to an alternate embodiment, a method of employing a plurality of integrated circuits in a multi-chip module comprises steps of configuring a plurality of programmable logic devices on a multi-chip module. A multi-chip integrated circuit package is also described.

Circuit for and method of implementing programmable logic devices

Described are methods for implementing customer designs in programmable logic devices (PLDs). The defect tolerance of these methods makes them particularly useful with the adoption of 'nanotechnology' and molecular-scale technology, or 'molectronics.' Test methods identify alternative physical interconnect resources for each net required in the user design and, as need, reroute certain signal paths using the alternative resources. The test methods additionally limit testing to required resources so devices are not rejected as a result of testing performed on unused resources. The tests limit functional testing of used resources to those functions required in the user designs.

Application-specific methods for testing molectronic or nanoscale devices

Disclosed methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected customer designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given customer design without requiring the vendor to understand the design.

Application-specific methods useful for testing look up tables in programmable logic devices

An integrated circuit receives an external clock signal and generates therefrom a clock signal that is supplied to a plurality of external devices. A delay-locked loop (DLL), a balanced clock tree, and a plurality of interface cells on the integrated circuit function together to supply the clock signal to the plurality of external devices such that the clock signal at each of the external devices is deskewed with respect to the external clock signal. Board level design is simplified because no balanced clock tree is needed to route the clock signal from the integrated circuit to the external devices, rather each external device is coupled to a corresponding one of the interface cells via a separate external connection. Each of these external connections has an equal propagation delay. One of the interface cells supplies the clock signal back to a reference signal input of the DLL via an external connection. This external connection has the same propagation delay as the external connections to the various external devices. Matching of the propagation delays of the various external connections may be accomplished by making the external connections all of the same length.

Deskewing clock signals for off-chip devices

The invention allows the implementation of common wide logic functions using only two function generators of a field programmable gate array. One embodiment of the invention provides a structure for implementing a wide AND-gate in an FPGA configurable logic element (CLE) or portion thereof that includes no more than two function generators. First and second function generators are configured as AND-gates, the output signals (first and second AND signals) being combined in a 2-to-1 multiplexer controlled by the first AND signal, &ldquo;0&rdquo; selecting the first AND signal and &ldquo;1&rdquo; selecting the second AND signal. Therefore, a wide AND-gate is provided having a number of input signals equal to the total number of input signals for the two function generators. In another embodiment, a wide OR-gate is provided by configuring the function generators as OR-gates and controlling the multiplexer using the second OR signal.

Multiplexer for implementing logic functions in a programmable logic device

Wide logic gate implemented in an FPGA configurable logic element

The invention provides a Configurable Logic Element (CLE) preferably included in each of an array of identical tiles. A CLE according to the invention has four function generators. The outputs of two function generators are combined with a fifth independent input in a five-input-function multiplexer or function generator to produce an output that can be any function of five inputs, or some functions of up to nine inputs. The outputs of the other two function generators are similarly combined. The outputs of the two five-input-function multiplexers or function generators are then combined with a sixth independent input in a six-input-function multiplexer or function generator. The six-input-function multiplexer or function generator therefore produces an output that can be any function of up to six inputs. Some functions of up to nineteen inputs can also be generated in a single CLE.

Configurable logic element with ability to evaluate wide logic functions

The invention provides an FPGA comprising an array of identical tiles. Each tile comprises a logic block that includes a Configurable Logic Element (CLE). In one embodiment, the CLE is implemented in two similar portions called 'slices'. Each slice has a separate carry chain. In a CLE with four function generators, each carry chain incorporates the outputs of two function generators.

FPGA CLE with two independent carry chains

Configurable logic element with ability to evaluate five and six input

The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. Each tile comprises a logic block that includes a Configurable Logic Element (CLE) and an output multiplexer. Fast feedback paths are provided within the logic block to connect the CLE outputs to the CLE inputs, either directly or through an input multiplexer. The fast feedback paths bypass the output multiplexer and therefore provide faster feedback than can be obtained in most conventional FPGA logic blocks. In one embodiment, the fast feedback paths provide the ability for all function generators in one CLE to drive each other through fast feedback paths, regardless of how logic is mapped into the function generators of the CLE.

Configurable logic element with fast feedback paths

According to the invention, a structure is provided for driving a bus line that is both fast and small. Instead of a plurality of tristate buffers, one for each input signal, a plurality of multiplexers or gates is connected into a tree structure. The tristate enable line of the tristate buffer becomes the control line for enabling the tree structure to place its own input signal onto the bus instead of propagating the signal already on the bus. A buffer element then allows the resulting signal to be tapped from the bus. One embodiment of the invention includes lookahead logic similar to a lookahead carry chain. This allows large numbers of input lines to be connected to a bus line while retaining high speed. The symmetrical delay of a tree structure minimizes the greatest delay and thus increases predicted speed.

Growing community of inventors

Cupertino, CA, United States of America

Shekhar Bapat