Cadence Design Systems, Inc.

Shekaripuram V Venkatesh

Karem A Sakallah

Robert J Palermo

Mohammad S Mortazavi

A computer-implemented method abstracts the timing constraints for latches internal to a digital logic circuit, resulting in a clock characterization model. Timing information (such as propagation delays, set-up and hold requirements) for latches and combinational logic circuits contained in a digital logic circuit are received, as is a description of a class of clock scheme for clocking the circuit. Clock parameters are selected for the clock scheme class. The internal timing constraints for the digital logic circuit are expressed as timing constraint expressions which are a function of the clock parameters. The expressions are combined to define a region of feasible clock operation expressed in terms of the clock parameters.

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San Jose, CA, United States of America

Shekaripuram V Venkatesh