At&t Bell Laboratories

Bell Telephone Laboratories

At+t Corp.

American Telephone & Telegraph Co., At&t Bell Laboratories

Sheila Vaidya

Robert L Kostelak, Jr

Joseph G Garofalo

Christophe Pierrat

William T Lynch

Ashok K Sinha

Hyman J Levinstein

Donald L White

Martin P Lepselter

Lalita Manchanda

Steven J Hillenius

Mark Richard Pinto

Tan T Sheng

Nadia Lifshitz

Eric L Raab

Ellis N Fuls

Through the use of a specifically configured buried dielectric region, devices with strict design rules, e.g., design rules of 0.9 micrometers and less, are significantly improved. In particular, the recessed dielectric region, e.g., field oxide, separating device areas in an integrated circuit, either has a buried conducting shield surrounding the periphery of the oxide or has a configuration such that the upper surface of the dielectric is no more than 20 nm below the upper surface of the silicon forming the device active region. By insuring a suitable configuration, parasitic capacitance resulting in slower operation is considerably reduced while leakage currents are maintained at an acceptable level.

Planar isolation technique for integrated circuits

In order to print an isolated feature having a width W in a photoresist layer using an optical radiation imaging system whose lateral magnification is equal to m, a phase-shifting mask is used having a corresponding isolated feature. In one embodiment this corresponding isolated feature has a central square portion having a refractive index n.sub.1 and a thickness t.sub.1, and a peripheral (rim) square-ring phase-shifting portion having a width B, as well as a refractive index n.sub.2 and a thickness t.sub.2, such that the phase-shift .phi.=2.pi.(n.sub.2 t.sub.2 -n.sub.1 t.sub.1)/.lambda. of the central portion relative to the peripheral portion is equal to .pi. radian or odd multiple integral thereof. The width C of the central portion advantageously is selected such that mC/W is equal to at least 1.2, and preferably greater than 1.5, rather than unity. In another embodiment, the isolated feature has an opaque central portion, also of width C, and a peripheral square-ring phase-shifting portion having a width B and having a phase-shift of .pi. radian relative to a surrounding transparent wide area ('bright field')--in which case, advantageously the value of m(C+2B)/W is equal to less than 1/(1.2), and preferably less than 1/(1.5).

Phase-shifting lithographic masks with improved resolution

A phase-shifting lithographic mask is fabricated, in one embodiment, by using a resist layer that is negative tone with respect to a (patterned) electron beam and is positive tone with respect to a (flood) mid-ultraviolet beam, with the tone of the electron beam predominating over that of the mid-ultraviolet beam. The resist layer is spun on a body comprising a patterned metallic layer located on a (transparent) quartz slab. The body is subjected from below to a flood mid-ultraviolet beam and from above to a patterned electron beam whose edges are located somewhere in the midst of the patterned opaque layer but are not coincident with any edges of the patterned opaque layer. Thus, a subsequent development of the resist layer removes those regions and only those regions of the resist layer upon which the ultraviolet beam was incident--i.e., not in the shadows cast by the patterned opaque layer--in the absence of incidence of the patterned electron beam. Then, an anisotropic etching removes to a prescribed depth the portions of the (transparent) substrate not covered by the remaining (patterned) resist layer. In other embodiments, the (patterned) electron beam is replaced by a (patterned) deep ultraviolet beam. In still other embodiments the same radiation (wavelength) can be used for the patterned beam as for the flood radiation in conjunction with a resist layer whose tone can be reversed by an intermediate processing step between irradiations with the patterned and flood beams, respectively.

Fabrication of phase-shifting lithographic masks

In an optical lithographical system (e.g., 100) for printing features of a patterned mask (e.g., 103) into a workpiece (e.g., 120), such as in a semiconductor device, a one- or two-dimensional (depending on the features of the mask) optical transmission phase-shift diffracting device (e.g., 107) is inserted between an optical condensor (e.g., 105) and the patterned mask whose features are to be printed into the workpiece. The diffracting device is designed so as to enable an imaging lens system (e.g., 102) to collect more than merely a single order of the resulting diffraction patterns of the features of the mask and, by varying the spatial periodicity of the diffracting device, to tailor the illumination incident on the mask in accordance with the features (e.g., 114, 115) of the mask.

Optical lithographical imaging system including optical transmission

A phase-shifting lithographic mask is made by a procedure involving only a single patterned electron, ion, or photon beam bombardment of a resist layer. The bombardment is arranged to produce three kinds of regions in the resist: no dosage, low dosage, and high dosage. These three regions in the resist are then utilized--in conjunction with an ordinary wet development step followed by either a silylation or an optical flooding technique, and thereafter by another ordinary wet development step--to pattern the resist layer and thereby to enable forming, by dry or wet etching, an underlying double layer consisting of a patterned opaque layer and a patterned transparent phase-shifting layer, the phase-shifting layer being located on, or being part of, a transparent substrate.

Single-alignment-level lithographic technique for achieving self-aligned

Phase-shifting (two-optical-level) masks are manufactured by a self-aligned technique in which after first-level trenches in the mask have been formed, second-level trenches therein are formed by patterning an electron resist overlying the mask in such a manner that the edges of the patterned resist can be located anywhere within the first-level trenches, whereby the need for precise alignment of the resist patterning for the second-level trenches is avoided.

Method of making phase-shifting lithographic masks

In order to reduce alignment errors arising in the fabrication of semiconductor integrated circuits using electron beam lithography, enhanced registration marks--(i.e., registration marks that are more easily and accurately detectable by the electron beam)--are formed at the edges of oxide layers, located at the surface of a silicon body, by means of forming metal silicide layers having edges coincident with the edges of the oxide layers. Advantageously, the enhancing of the registgration marks by forming the metal silicide is performed subsequent to any high temperature processing steps, whereby the integrity of the marks is maintained.

Self aligned registration marks for integrated circuit fabrication

A resistive load element comprises a Schottky barrier metal layer formed on the top surface of a doped p-type polycrystalline silicon (polysilicon) plug contacting a surface n.sup.+ zone located in a semiconductor body at a major horizontal surface thereof. The Schottky barrier metal layer is advantageously essentially a metal compound, such as titanium nitride, which does not react with the polysilicon and which forms a Schottky barrier contact with the polysilicon top surface of the plug. The polysilicon plug extends vertically down to the n.sup.+ zone through an aperture in an insulating layer that coats the major surface of the semiconductor body. The top surface of the Schottky barrier layer is coated with another metal layer, such as aluminum, for interconnection purposes. A pair of such elements can be integrated as loads, for example, in a static random access memory ('flip-flop') cell.

Semiconductor integrated circuit vertical geometry impedance element

For optimal performance, the threshold voltages V.sub.TP and V.sub.TN of the p- and n-channel transistors in a CMOS device should be the respective complements of each other. In polysilicon-gate devices, this can be achieved by adjusting the corresponding gate-metal work function utilizing p.sup.+ and n.sup.+ polysilicon for the respective gates of the p- and n-channel transistors. However, when a refractory metal silicide-over-polysilicon gate structure is employed in a VLSI CMOS device in which the gates of a pair of adjacent complementary transistors are connected together, an anomalously large negative V.sub.TP is measured. The invention is a unique process sequence that achieves substantially complementary p- and n-channel transistor thresholds in a high-speed VLSI CMOS device that includes silicide-over-polysilicon gates.

Method of fabricating VLSI CMOS devices having complementary threshold

In an MOS integrated circuit device, a multilayer polysilicon/metallic-silicide gate-level metallization structure is patterned to form gates and associated interconnects. Some of the interconnects are designed to make contact with ohmic regions in the single-crystalline body of the device. In accordance with a simplified fabrication procedure, a single implantation step is utilized to dope the metallic silicide while doping selected portions of the body. During a subsequent heating step, source, drain and ohmic contact regions are formed in the body. During the same step, the dopant in the metallic silicide diffuses into underlying layers of polysilicon and into body portions directly underlying polysilicon in amounts sufficient to render the polysilicon conductive and to form additional ohmic contact regions in the body.

Fabrication of MOS integrated circuit devices

Aluminum electrically conducting patterns for integrated circuits are achieved with narrow lines and unexpectedly-high electromigration characteristics by making the crystal grains of the pattern into a chain-shaped structure with {111} orientation. A process for achieving the structure is also described.

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Watchung, NJ, United States of America

Sheila Vaidya