Freescale Semiconductor,inc.

Nxp Usa, Inc.

Sheila F Chopin

Varughese Mathew

Leo M Higgins, Iii

Chu-Chung Lee

Scott S Roth

Peter R Harper

Boon Yew Low

Tu-Anh N Tran

Nishant Lakhera

Susan H Downey

Alan H Woosley

Yuan Yuan

Min Ding

Perry H Pelley

Yaping Zhou

Thomas H Koschmieder

Nhat Dinh Vo

Peng Su

Sohrab Safai

An encapsulant compound apparatus, includes a mechanical operator, and an insert disposed on a surface of the mechanical operator. The insert operates to capture foreign material in the encapsulant compound.

Conduit inserts for encapsulant compound formulation kneading and encapsulation back-end assembly processes

The present disclosure provides for embodiments of packaged semiconductor devices. In one embodiment, a packaged semiconductor device for a die includes an exposed structure. The die has an active surface and a backside surface opposite the active surface. A first surface of the exposed structure is joined to die attach material, and the die attach material is further joined to the backside surface of the die. The exposed structure includes a plurality of openings through the exposed structure within a perimeter of the die, and the die is exposed through the plurality of openings.

Semiconductor device attached to an exposed pad

A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.

Semiconductor structure with sacrificial anode and method for forming

A method of manufacturing a packaged semiconductor device includes patterning and plating silver nanoparticles in bonding areas of a lead frame, forming a hydrophilic group while oxidizing the silver nanoparticles, forming wire bonds on the silver nanoparticles, and encapsulating the wire bonds and the silver nanoparticles.

Packaged semiconductor device with a lead frame and method for forming

A method of forming an electronic component includes masking a lead frame to form a mask defining an exposed area, oxidizing the exposed area of the lead frame, wherein the mask inhibits oxidation of an unexposed area, and removing the mask from the lead frame following oxidizing. A lead frame can include a metal sheet patterned to define a pad region and leads. The metal sheet includes metal oxide in a select area. The pad region is substantially free of metal oxide.

System and method for lead frame package degating

Semiconductor structure with sacrificial anode and passivation layer and method for forming

A method includes forming a packaged integrated circuit that includes forming a lead frame by separating an outer portion of the metal structure into a plurality of leads by stamping. The plurality of leads have sides with a first concavity. The lead frame is further formed by performing an etch on the sides of the plurality of leads to achieve a second concavity on the sides of leads. The second concavity is greater than the first concavity. A semiconductor die is attached to a center portion of the metal structure. Electrical attachments are made between the die and the leads.

Semiconductor device

A mold compound is provided for encapsulating a semiconductor device (). The mold compound comprises at least approximately 70% by weight silica fillers, at least approximately 10% by weight epoxy resin system, and beneficial ions that are beneficial with respect to copper ball bond corrosion. A total level of the beneficial ions in the mold compound is at least approximately 100 ppm.

Encapsulant for a semiconductor device

A technique for testing the compatibility of an encapsulation material and a wire bond included at an unencapsulated assembly. The technique includes immersing the assembly in an encapsulating compound extract. The assembly includes a semiconductor die and a bonding wire affixed to a metalized pad of the semiconductor die by the wire bond. After the immersing, a mechanical strength of the wire bond is determined.

Mold compound compatibility test system and methods thereof

A packaged semiconductor device includes a package substrate, an integrated circuit (IC) die mounted on the package substrate, and a heat spreader mounted on the package substrate. The heat spreader surrounds at least a portion of the IC die and includes a lid with a plurality of openings. An inner portion of the heat spreader includes a plurality of thermally conductive protrusions adjacent the die.

Heat spreader for use within a packaged semiconductor device

A method for curing an encapsulant that surrounds a plurality of integrated circuits on a strip that forms a strip assembly is provided. The strip assembly is composed of units for packaging and the units each have edges defining a perimeter of the unit. The strip assembly is placed on a shelf. Pressure from deformable material or springs is applied to the strip assembly in regions of the strip. The regions are located at one of a group of locations consisting of along unit edges and centered between unit edges. Heat of sufficient temperature is applied for a sufficient duration to cure the encapsulant. The step of applying pressure continues during the application of heat for curing.

Warpage control using a package carrier assembly

A packaged integrated circuit includes a die surrounded by an encapsulant in which leads are used to electrically connect the die, which is internal to the encapsulant, externally. The leads have a primary metal that is used for electrical conduction and physical support. The external portion of the lead is coated with another metal, typically tin, that is useful for soldering. This tin layer is formed in a manner that ensures that it is porous. Although porous is generally thought to be a bad characteristic, it turns out to be very effective in absorbing stress and thus retarding whisker growth. Whisker growth, which can short adjacent leads together as well as cause other deleterious effects, has been a major source of failures in packaged integrated circuits. An additional layer of very thin tin that is non-porous can be added before or after the porous tin layer has been deposited.

Solderable metal finish for integrated circuit package leads and method for forming

During the curing process of the package strips, especially during post encapsulant cure (PEC), undesirable warpage of package strips occurs. A carrier having angled lands and side-insertion clamp structures with angled clamp fins may be used to control this cure-induced warpage of package strips during PEC. In one embodiment, the angled lands and angled side-insertions clamps are used to clamp the edges of the package strip in order to introduce an intentional deformation which counters warpage which occurs during PEC. The angled lands and side-insertion clamps may be at any angle (fixed or adjustable). The side-insertion clamps may be inserted before or after insertion of the package strips into the carrier. Once the package strips are in the carrier and resting on the angled lands, a force may be applied to the side-insertion clamps to clamp the edges of the package strips between a clamp fin and an angled land.

Growing community of inventors

Austin, TX, United States of America

Sheila F Chopin