Apple Inc.

Sheenam Jayaswal

Terence M Potter

Benjiman L Goodman

Yoong Chert Foo

Anjana Rajendran

Roman Tereshin

Rohit Kumar Singh

Techniques are disclosed relating to graphics processor that support ray tracing. In particular, shader circuitry may be configured to adjust a scheduling priority of a single-instruction multiple-data (SIMD) group of a shader program based on a hint that the SIMD group has an upcoming ray intersect command for ray intersect accelerator circuitry and based on a resource usage indication from the ray intersect accelerator circuitry. This may advantageously reduce cache thrashing, e.g., when shaders may allocate memory for ray intersect commands and fill a shared cache faster than the ray intersect accelerator circuitry can process the rays.

Hint for scheduling graphics ray tracing work

Techniques are disclosed relating to multi-stage thread scheduling. In some embodiments, processor circuitry includes multiple channel pipelines for multiple channels and multiple execution pipelines shared by the channel pipelines and configured to perform different types of operations provided by the channel pipelines. First scheduler circuitry may arbitrate among threads to assign threads to channels. Second scheduler circuitry may arbitrate among channels to assign an operation from a given channel to a given execution pipeline. The execution pipelines may provide backpressure information to the first scheduler circuitry based on execution status and the first scheduler circuitry may adjust priority of a thread for assignment to a channel based on the backpressure information. Disclosed techniques may reduce channel conflicts and starvation for execution resources.

Multi-stage thread scheduling

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Austin, TX, United States of America

Sheenam Jayaswal