Freescale Semiconductor,inc.

Nxp Usa, Inc.

Freescale Semiconducotr, Inc.

Shayan Zhang

Andrew Christopher Russell

Prashant U Kenkare

Bradford Lawrence Hunter

James David Burnett

Michael D Snyder

Troy L Cooper

Ravindraraj Ramaraju

Wanggen Zhang

David R Bearden

William C Moyer

Jack M Higman

Yin Guo

Jianan Yang

Scott Ives Remington

Wenzhong Zhang

Hema Ramamurthy

Xu Zhang

Sian Lu

Jing Cui

Kent P Fancher

Hector Adrian Sanchez

Alexander Hoefler

Mohit Arora

Kenneth R Burch

Klas Magnus Bruce

Nihaar N Mahatme

Rakesh Pandey

Zheng Xu

Charles Eric Seaberg

Brad John Garni

Ling Wang

Lei Zhang

Yizhong Zhang

Huy Nguyen

Huangsheng Ding

Xiaoxiang Geng

David Burnett

Hao Wang

Xiuqiang Xu

Kun Wu

Yi Zhao

Mingqin Xie

Xuewen He

Yong Zhu

Yunwu Zhao

Wen Gu

Ziyu Guo

Xiangming Kong

Baiquan Shen

Guoping Wan

Haifeng Bai

Chad J Lerma

Kai Liu

Pelley H Perry

Ravindraj Ramaraju

Karen Delk

A read only memory (ROM) having a first row of ROM cells, a first conductive line along the first row of ROM cells, and a second conductive line along the first row of ROM cells. The ROM cells of the first row of ROM cells are selectively coupled during programming to the first conductive line and the second conductive line so that in a first mode of the ROM the first row of ROM cells provide a first combination of logic highs and logic lows and in a second mode of the memory the first row of ROM cells provide a second combination of logic highs and lows independent of the first combination of logic highs and logic lows.

Memory array with read only cells having multiple states and method of programming thereof

A method of secure key generation includes writing a predetermined write pattern to a particular address of volatile memory, wherein the volatile memory includes bit lines; reading data from the particular address while applying a first set of operating variables to the volatile memory, subsequent to the writing; sensing a first plurality of timing mismatches during the reading, wherein sense amplifiers are coupled to the bit lines, each latch of a plurality of latches is coupled between a respective pair of sense amplifiers, and each latch is configured to output a data value that indicates a respective timing mismatch between outputs of the respective pair of sense amplifiers; and determining an entropy ratio for the particular address, wherein the entropy ratio is equivalent to a ratio of a first number of latches that output a first data value to a second number of latches that output a second data value.

Data processing system with secure key generation

A memory device having at least one output predicting a feasibility of whether the memory device will work properly at a different operating condition including a different supply voltage and/or a different operating frequency than the current supply voltage and/or the current operating frequency. A semiconductor device (e.g. a SoC chip) provides a test to either validate or invalidate the feasibility for the memory device to enter such a different operating condition based on read and write operations of the memory device in normal access cycles. The memory device is partitioned with at least a first memory unit and a second memory unit, which can be coupled to different back-bias voltages. This operating condition predicting function can be enabled or disabled by the semiconductor device in real time operation depending on the feasibility test results.

Method and apparatus for determining feasibility of memory operating condition change using different back bias voltages

An integrated circuit that includes a processor also has an on-chip current test circuit that indirectly measures quiescent current in the processor. A supply voltage pin of the integrated circuit receives a supply voltage from an external test unit to provide power to the processor. The on-chip test circuit measures a voltage change across the processor during a predetermined test period T when the processor is isolated from the supply voltage and the clock signal is stopped. The voltage change provides an indication of quiescent current corresponding to the processor.

On-chip current test circuit

A memory array with RAM and embedded ROM including multiple RAM cells, a ROM cell, and a ROM enable circuit. Each RAM cell has a RAM cell structure with a first and second power terminals and configured to operate as a RAM cell when the memory array is in a RAM mode. The ROM cell has the same RAM cell structure in which at least one transistor is modified to cause the ROM cell to have a predetermined logic state. The ROM enable circuit enables bit lines of the ROM cell to control supply voltages provided to the power terminals of the RAM cells so that they settle to predetermined logic states in a ROM mode. The modified transistor has a pseudo transistor structure having a modified substrate that operates as a resistance, such as a doping region in the substrate having the same polarity type as the substrate.

Memory array with RAM and embedded ROM

An integrated circuit (IC) and associated method support using a pre-use configuration for determining an initial/preferred operational mode for the IC from plural operational modes that may be entered following power-up cycles of the IC. The initial/preferred operational mode can be determined after the design phase of the IC so that, during IC operation, wasted power or delay are not incurred by first requiring that the IC power up in a default operational mode and subsequently run executive code to reprogram the IC to enter an operational mode that is preferred for the application for which the IC is being used by the IC integrator/user. The configurations determine clock frequencies and/or power levels for core processing and/or peripheral modules and allow the same IC design/die to be targeted to a spectrum of different power usage/performance applications by the integrator/user.

Integrated circuit with selectable power-on reset mode

A BIST circuit is provided for testing the status of power supplies in an integrated circuit in multiple power modes including multiple circuit blocks. The BIST circuit includes a finite state machine (FSM), power monitors and a comparator. The FSM sequentially enables at least two power mode states in a predetermined order. In each power mode state, the FSM outputs power mode signals to enable the power supplies used in the corresponding power mode. Each power monitor is connected to a power input node of one of the circuit blocks, and outputs a monitor signal indicative of the voltage at the corresponding power input node when the corresponding power supply is enabled. The comparator compares each monitor signal with a corresponding reference signal and generates a set of power supply status signals.

Circuit for testing power supplies in multiple power modes

A controller for a memory device has a power control section to control power to a memory element in an operation mode and in a retention mode. A monitoring section receives and monitors error information and a storage section stores a retention parameter. In the operation mode, the power control section causes an operation voltage to be applied to the memory element, and in the retention mode, the power control section causes a time-varying voltage to be applied to the memory. The power control section also causes the voltage across the memory element to change in the retention mode between a first retention voltage and a second retention voltage based on the retention parameter.

Memory device retention mode based on error information

A semiconductor memory device and method of operation are provided for a multi-bank memory array () with an address fault detector circuit () connected to split word lines (WLn-WLm) across multiple banks, where the address fault detector circuit includes at least a first MOSFET transistor (-) connected to each word line for detecting an error-free operation mode and a plurality of different transient address faults including a 'no word line select,' 'false word line select,' and &#x201c;multiple word line select&#x201d; failure mode at one of the first and second memory banks. In selected embodiments, the address fault detector provides resistive coupling (-) between split word lines across multiple banks to create interaction or contention between split word lines to create a unique voltage level on a fault detection bit line during an address fault depending on the fault type.

Address fault detection circuit

Power control circuitry for a data processor supplies a memory array with a supply voltage corresponding to a memory performance level. The performance levels include a full performance level and a power-saving performance level. Voltage sensing circuitry senses a voltage level of the memory array and outputs a power status signal. The power status signal is used to determine when the memory array is awake and can be accessed.

Performance based power management of a memory and a data storage system using the memory

A digital decoder, used in a reconfigurable circuit, for decoding digital pulses includes a phase indicator module having inputs coupled to a reference pulse input and a data pulse input. The phase indicator module has timing information outputs that provide logic values indicative of rising and falling edges of pulses occurring on the reference pulse input and the data pulse input. A phase decoder module has inputs coupled to the timing information outputs, and outputs decoded binary data values. In operation, the phase decoder module compares at least two of the logic values at the timing information outputs with a signal representative leading and trailing edges of a pulse applied to one of the phase inputs to determine a pulse arrival order sequence on the phase inputs and thereby provide the decoded binary data values.

Reconfigurable circuit and decoder therefor

An amplifier applies a self-adapting voltage to an output terminal. A bias circuit provides a greater bias current in a first external connection condition, in the absence of a pull-up resistance connected to the output terminal, than when such a pull-up resistance is present. The amplifier applies a different voltage to the output terminal in the absence of a pull-up resistance than when such a pull-up resistance is present. The circuit can be used in a portable device for receiving charging current from a battery charger through a connector having a D+ pin for connection to the battery charger and connected to the amplifier output terminal for battery charger detection. The portable device can meet the USB battery charger specification rev. 1.2.

Self-adapting voltage amplifier and battery charger detection

A low power State Retention Power Gating (SRPG) cell has a retention component and a non-retention component, and is operable in a run state, a first retention state, and a second retention state. In the run state, the retention and non-retention components are powered with a supply voltage. In the first retention state, the retention component is powered at the same supply voltage as in the run state, and the non-retention component is powered down. In the second retention state, the retention component is powered at a lower supply voltage than in the run state, and the non-retention component is powered down.

Low power SRPG cell

A configurable flip-flop can be operated in a normal mode and a buffer mode. In the normal mode, the flip-flop latches data at the flip-flop input based on a clock signal. In the buffer mode, the flip-flop provides data at the flip-flop input to the flip-flop output, independent of the clock signal.

Configurable flip-flop

A system for performing a scan test on an integrated circuit such as a System on a Chip (SoC) that may be packaged in different package types and with different features enabled includes a bypass-signal generator and a first scan-bypass circuit. The bypass-signal generator generates a first bypass signal based on chip package information. The first bypass signal indicates whether a first scan chain associated with a first non-common circuit block of the SoC is to be bypassed. The first scan chain is bypassed in response to the first bypass signal. By enabling partial scan testing based on package information, unintentional yield loss caused by a full scan test determining an SoC is faulty can be avoided.

System and method for performing scan test

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Austin, TX, United States of America

Shayan Zhang