Huawei Technologies Co., Limited

Alphawave IP Inc.

Shayan Shahramian

Behzad Dehlaghi

Ryan Douglas Bespalko

Euhan Chong

Anthony Chan Carusone

James Raymond Bailey

Ming Yang

A receiver for providing a corrected output symbol sequence is disclosed. A decision feedback equalizer (DFE) generates an output sequence of DFE decision symbols; a second feed forward equalizer (FFE) generates a second equalized output symbol sequence; and correction logic, responsive to determination of an end of burst error position of a burst error sequence in the DFE output sequence, determines a candidate earliest start of burst position, and determines the corrected output symbol sequence by comparing the second equalized output symbol sequence with candidate symbol sequences that correspond to corrections of DFE decision output symbols in the burst error sequence.

Burst error detection and correction

Methods and apparatuses for calibrating voltage offset of receiver data samplers in mission mode are described. The operating conditions, including the sampling threshold, of a first sampler are matched with those of a second sampler by adjusting the voltage offset of the second sampler. The voltage offset of the first sampler is adjusted in a first voltage direction until an error rate between the two samplers meets a threshold error value at a first threshold voltage offset value. The voltage offset of the first sampler is further adjusted in a second voltage direction, opposite of the first voltage direction, until the error rate between the two samplers meets the threshold error value at a second threshold voltage offset value. The voltage offset of the first sampler is adjusted to be an average value between the first threshold voltage offset value and the second threshold voltage offset value.

System and method for continuous sampler calibration

The disclosed systems, structures, and methods are directed to a method for determining a set of N optimal coefficients to be supplied to an equalizer, the equalizer being employed in at least one of a serializer and a deserializer, the method comprising: receiving N different parameters, searching an initial set of N coefficients on an N-dimensional performance surface, in accordance with a genetic algorithm, wherein the N-dimensional performance surface corresponds to various coefficients in the N parameters, and fine tuning the initial set of N coefficients to provide the set of N optimal coefficients, in accordance with a gradient descent algorithm.

Method and apparatus for determining a set of optimal coefficients

The present disclosure relates to a 1/K-rate decision feedback equalizer (DFE) and to a decision feedback equalization method. The DFE comprises: (i) a summing circuit configured to combine K intersymbol interference (ISI) cancellation signals with an input signal of the DFE, (ii) K branches each including a reset-to-zero (RZ) latch configured to receive an output signal of the summing circuit according to a clock signal and to produce a RZ signal, and (iii) a feedback circuit including K filters each configured to receive a respective RZ signal from a respective RZ latch and to produce a respective ISI cancellation signal. The method comprises: (i) producing an output signal for K branches based on K cancellation signals and on an input signal, (ii) producing K RZ signals based on the output signal and on a clock signal, and (iii) producing the K ISI cancellation signals based on the K RZ signals.

Decision feedback equalizers and methods of decision feedback equalization

The present disclosure relates to a receiver and to a method implemented in the receiver for recovering a signal clock from a received data signal. Successive edge transitions between successive data samples of the received data signal are detected according to a clock recovered in the receiver. The recovered clock is adjusted based on a combination of weights assigned to at least some edge transitions among the plurality of successive edge transitions. In particular, (i) each very early transition is assigned a first weight having a first sign, (ii) each early transition is assigned a second weight having the first sign, (iii) each late transition is assigned a third weight having a second sign opposite from the first sign, and (iv) each very late transition is assigned a fourth weight having the second sign.

Receiver recovering a signal clock from a received data signal, and a clock recovery method implemented in the receiver

Described herein is a termination circuit for a receiver receiving a single-ended signal. The termination circuit includes the first stage having a low-pass transfer function having a first pole/zero pair, and a second stage coupled to the first stage, where the second stage has a high-pass transfer function having a second pole/zero pair that cancels out the first pole/zero pair.

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Richmond Hill, Canada

Shayan Shahramian