Xilinx, Inc.

Shay Ping Seng

Chi Bun Chan

Nabeel Shirazi

Jingzhao Ou

Jonathan B Ballagh

Roger Brent Milne

L James Hwang

Bradley L Taylor

Arvind Sundararajan

Haibing Ma

Amit Kasat

Jeffrey Stroomer

Adam P Donlin

Paul Mobbs

Sean Kelly

Khang Kim Dao

Jeffrey H Seltzer

Kyle Corbett

William Edward Allaire

Bradley K Fross

Srinivas Beeravolu

Alexander Carreira

Christopher J Case

Krishnan Subramanian

Robert E Shortt

Biping Wu

Jing Zhao Ou

Methods for generating a circuit design are disclosed. A plurality of cells is instantiated in the circuit design in response to user input. The set of interface parameters of each cell is arranged into a hierarchy of interface levels as indicated by an interface model corresponding to the cell. For each of the interface levels, values of the sets of interface parameters of cells included in the interface level are respectively propagated to other cells directly connected to the cell. In response to propagating a value of an interface parameter from another cell of the plurality of cells to the cell and the cell having a value of the corresponding interface parameter that is different from the propagated value, a value for the corresponding interface parameter of the cell is determined using a respective propagation function associated with the corresponding interface level.

System level circuit design

A method of circuit design includes receiving a user input selecting a first interface of a circuit block of a circuit design as a source interface in creating a connection within the circuit design and selecting a second interface of the circuit design as a candidate destination interface for the connection using a processor. The method further includes determining compatibility between the second interface and the first interface and indicating compatibility of the second interface with the first interface for the connection.

Electronic design automation tool for guided connection assistance

A method of performing a simulation of a design under test is disclosed. The method comprises implementing an input block having an adjustable output width; coupling test data to the input block; generating an input signal comprising the test data for the design under test according to an input requirement for the design under test by way of the input block; implementing an output block having an adjustable input width for receiving data from an output of the design under test; and coupling the output of the design under test to the output block according to an output requirement of the design under test. A circuit for enabling testing of a circuit design implemented in an integrated circuit is also disclosed.

Method of performing a simulation of a design under test and a circuit for enabling testing of a circuit design

A method and apparatus for providing a program-based hardware co-simulation of a circuit design are described. In one example, a circuit design is implemented for programmable logic to establish a design under test (DUT). A co-simulation model is programmatically generated using primitives defined by an application programming interface (API). The circuit design is simulated by configuring the programmable logic with the DUT and driving a co-simulation engine to communicate with the DUT via execution of the co-simulation model.

Method and apparatus for providing program-based hardware co-simulation of a circuit design

A method is provided for generation of a circuit design. A set of design assistance rules is retrieved from a database. Each design assistance rule in the set includes a list of design objects to which the design assistance rule applies, a set of criteria to be satisfied by the circuit design before the design assistance rule may be applied, a set of configuration options, and an executable script configured to perform an automated configuration of the circuit design. In response to a change in the circuit design, applicable design assistance rules are determined based on the corresponding sets of criteria. In response to determining that one or more design assistance rules are applicable, data indicating that the one or more design assistance rules are available is output. In response to input that selects a design assistance rule the executable script corresponding to the selected design assistance rule is executed.

Assistance tool

A high-level integrated circuit ('IC') modeling system () includes a first co-simulator () modeling a first portion of an IC system and a second co-simulator () modeling a second portion of the IC system, each co-simulator operating according to initial simulation operating conditions (). A co-simulation synchronization interface () is configured to automatically change at least one of the initial simulation operating conditions to a triggered operating condition () in response to a user-selected triggering signal.

Co-simulation synchronization interface for IC modeling

Method and apparatus for modeling processor-based circuit models are described. Some examples relate to designing a circuit model having a processor system and custom logic. A bus adapter coupled to a bus of the processor system is generated. A shared memory interface between the custom logic and the bus adapter is generated. The shared memory interface includes a memory map for the processor system. A clock wrapper having a first clock input and a second clock input is generated. The first clock input drives the custom logic and first shared memory of the shared memory interface. The second clock input drives the processor system.

Method and apparatus for modeling processor-based circuit models

A method of managing programmable device configuration can include running a server configuration image within the programmable device and storing a different configuration image within a non-volatile memory communicatively linked with the programmable device. Responsive to a switch request sent from the client to the programmable device over the communications link, the different configuration image can be loaded into the programmable device.

Managing programmable device configuration

Approaches for preparing simulation models of an electronic circuit are disclosed. The design is partitioned into first and second clusters. The design includes a source module in the first cluster connected to a destination module in the second cluster. The first cluster is compiled into a first model for a software-based co-simulation platform for simulating behavior of the source module using the first model. The first cluster and the second cluster of the design are compiled into a second model for a hardware-based co-simulation platform that includes a programmable logic circuit configurable for emulating behavior of the design using the second model. An interconnection block is generated and stored in the second model. The interconnection block is switchable between coupling of the destination module in the second model to the source module of the first model or to a source module of the second model.

Clustering of electronic circuit design modules for hardware-based and software-based co-simulation platforms

An interface to a dynamically configurable arithmetic unit can include data alignment modules, where each data alignment module receives input variables being associated with one or more arithmetic expressions. The interface can include multiplexers coupled to the data alignment modules, wherein a data alignment module has outputs coupled to a first multiplexer. The first multiplexer can have a selection line and an output coupled to an input port of the dynamically configurable arithmetic unit. The interface can include a second multiplexer having input instructions and the selection line, where each instruction is associated with one of the arithmetic expressions and has an operation to be performed by the dynamically configurable arithmetic unit. The second multiplexer is configurable to provide selected ones of the input instructions to the dynamically configurable arithmetic unit through an output of the second multiplexer responsive to the selection line.

Interfacing with a dynamically configurable arithmetic unit

An integrated circuit configured for hardware co-simulation can include a command processor, a replay buffer storing a command template, wherein the command template specifies an incomplete command, and a command first-in-first out (FIFO) memory storing complementary data for completion of the command template. The integrated circuit further can include a multiplexer coupled to the command processor, the replay buffer, and the command FIFO. The multiplexer, under control of the command processor, can selectively provide data from the replay buffer or the command FIFO to the command processor. The command processor, responsive to a replay command read during a hardware co-simulation session, can enter a replay mode, obtain the command template from the replay buffer, obtain the complementary data from the FIFO memory according to a symbol read from the command template, and form a complete command by joining the command template with the complementary data.

Accelerating hardware co-simulation using dynamic replay on first-in-first-out-driven command processor

A method of passing data among modules of a heterogeneous software system can include identifying a scripted function to be executed within the heterogeneous software system and building a wrapper script by embedding a call to the scripted function and an XTable object associated with the scripted function within the wrapper script. The method further can include executing the wrapper script thereby causing the scripted function to execute and receiving a result from execution of the scripted function.

Using scripts for netlisting in a high-level modeling system

A method of implementing a circuit design on a programmable integrated circuit can include displaying a list of at least one memory of the circuit design that is associated with the processor. A plurality of attributes of an event for the processor can be received. The plurality of attributes can specify a condition that, when met within at least one memory from the list, causes a signal to be generated to the processor. A description of an event interface for the processor can be automatically created according to the plurality of attributes of the interrupt. The description of the event interface can be incorporated into a description of the circuit design.

Processor event interface for programmable integrated circuit based circuit designs

Generation of a circuit design using a command language. The various approaches include generating in a memory arrangement respective instances of design blocks in response to user-entered commands that specify creation of the instances. Matrix-relative positions of the instances of design blocks are established in the memory arrangement in response to at least one user-entered command that specifies respective matrix positions of the instances. Representative connections between the instances are generated in the memory arrangement in response to a user-entered command having no specification of the connections.

Generation of a circuit design from a command language specification of blocks in matrix form

Method, apparatus, and computer readable medium for circuit design is described. In one example, a model having at least one processor, at least one logic, and at least one shared memory is specified. The at least one shared memory is associated with the at least one processor. A memory map associated with the at least one shared memory and a bus adapter for coupling the memory map to the at least one processor are automatically generated.

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San Jose, CA, United States of America

Shay Ping Seng