Intel Corporation

Shay Levy

Efraim Rotem

Eliezer Weissmann

Nir Rosenzweig

Yevgeni Sabin

Doron Rajwan

Yoni Aizik

Hisham Abu Salah

Gal Leibovich

Esfir Natanzon

Hisham Abu-Salah

Daniel D Lederman

In an embodiment, a processor for demotion includes a plurality of cores to execute instructions and a demotion control circuit. The demotion control circuit is to: for each core of the plurality of cores, determine an average count of power state break events in the core; determine a sum of the average counts of the plurality of cores; determine whether the average count of a first core exceeds a first demotion threshold; determine whether the sum of the average counts of the plurality of cores exceeds a second demotion threshold; and in response to a determination that the average count of the first core exceeds the first demotion threshold and the sum of the average counts exceeds the second demotion threshold, perform a power state demotion of the first core. Other embodiments are described and claimed.

Controlling power state demotion in a processor

In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.

Controlling performance states of processing engines of a processor

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Zicjron Yaakov, Israel

Shay Levy