Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Westem Digital Technologies, Inc.

Shay Benisty

Ariel Navon

Yehuda Hahn

Alexander Bazarsky

Amir Segev

Tal Sharifie

Alon Marcu

Eran Sharon

Elkana Richter

Karin Inbar

Yair Baram

Alex Bazarsky

Ran Zamir

Dudy David Avraham

Yoav Weinberg

Leonid Minz

Amir Rozen

Ishai Ilani

Avichay Haim Hodes

Rajesh Koul

Noga Harari Shechter

Idan Alrod

William Bernard Boyle

Daniel Joseph Linnen

Julian Vlaiko

Opher Lieber

Nissim Elmaleh

Vitali Linkovsky

Yoseph Hassan

Eran Erez

Yuri Ryabinin

Itshak Afriat

Michael James

Aki Bleyer

Erez Frank

Klod Assulin

Tomer Geron

Stephen Gold

Tomer Tzvi Eliash

Chinnakrishnan Ballapuram

Dmitry Vaysman

Tomer Eliash

Scheheresade Virani

Ofir Pele

James J Walsh

Yan Dumchin

Girish Desai

David Meyer

Marcus A Carlson

Eran Moshe

Rotem Sela

William Guthrie

Kan Lip Vui

Yuval Yoskovits

Ilya Gusev

Simon Bass

Eran Banani

Yossi Yoseph Hassan

Guruswamy Ganesh

Beniamin Kantor

Yevgeny Zagalsky

Oded Karni

Amit Alon

Moshe Karni

Alexey Martynenko

Adi Blum

Klod Ausslin

Amir Turjeman

Gennady Burdo

Yevgeny Lazarev

Different operations have different clock rate bottleneck points. For example, during a read operation, the processors may be the bottleneck whereas other operations will not be bottlenecks. Those other operations can have their clock rates reduced to save power since there is no benefit to a higher clock rate as the bottleneck is elsewhere. Predicting the bottleneck would be beneficial. Statistics correlating the bottleneck points with the workload and clock rates are tracked. When the workload changes, the statistics can be consulted to determine where the bottleneck is located and then slow down the clock rates for the non-bottleneck operations. A clock rate table is maintained in the device controller. The table holds the clock rate of each component. Predicting the workload and hence, the clock rates, reduces power consumption, improves performance, and better quality of service (QOS) compatibility characteristics.

Adaptive tuning of memory device clock rates based on usage workloads

Identical address mapping for data and metadata can be used to support either data integrity extension (DIX) format or data integrity field (DIF) format. To do so, the data storage device is responsible for generating and maintaining scatter gather lists (SGLs). The data storage device can maintain either a DIX format or a DIF format in a host memory buffer (HMB) and then convert from DIX format to DIF format if the host device uses DIF format. Conversely, the data storage device can convert from DIF format to DIX format if the host device uses DIX format. Extending DIF capability to DIX capability, and vice versa, is possible without any changes to data flow.

Converting DIX to DIF using HMB buffer management

Scanning overlap tables for data that is present in cache, but not yet written to the memory device, is time consuming. Performance requirements are increasing as is the size of the overlap table. With the increased size of the overlap table comes a reduction in speed to obtain results of a scan which leads to challenges meeting performance requirements. By providing a cache occupation bitmap, scans can be reduced. Rather than scanning the entire overlap table, a cache occupation bitmap can be searched. When executing a read command, only if the cache occupation bitmap contains an indication that the overlap table has cache data within a range that encompasses the data correlating to the read command will the overlap table be search. In so doing, the overlap table need not be searched when executing every read command, thus allowing achievement of performance requirements more realistic.

Selective scanning of overlap-table in storage memories

Systems, methods, and data storage devices for secured failover access through data storage device side channels are described. Storage devices may include a storage interface and one or more side channels, such as control bus and debug bus interfaces. The different interfaces may use different interface protocols and physical interface connections configured for different types of commands to the data storage device. When a failure of the storage interface occurs, the data storage device may receive a failover message through one or more side channels to reconfigure the side channel interface to receive, execute, and return a response for host storage commands targeting host data on the storage medium.

Secured failover access through data storage device side channels

A system and method are disclosed for flexible emergency power fail management for multiple persistent memory regions. In one embodiment, a method is provided that is performed in a host in communication with a plurality of data storage devices, each data storage device having a persistent memory region, wherein the host comprises a capacitor shared by the plurality of data storage devices. The method comprises determining an allocation of power from the capacitor to each of the plurality of data storage devices; and dynamically changing the allocation of power from the capacitor to at least one data storage device of the plurality of data storage devices. Other embodiments are disclosed.

System and method for flexible emergency power fail management for multiple persistent memory regions

Logical to physical (L2P) tables are implemented in solid state drives (SSDs) to hold L2P address translations. In a thin provisioning or thin storage system, the L2P table is sized to support the total amount of memory that is available to be allocated on a per client or per host basis. During thin provisioning, the total amount of memory is not typically utilized. As such, the L2P table, which is sized to accommodate full usage of the memory allocated, is not fully utilized resulting in unused portions of the L2P table. The unused portions of the L2P table can be reallocated to use as temporal buffers until needed for write commands. Due to the reallocation, less buffers are needed.

Thin provisioning L2P resource sharing

When entering low power mode, any commands that are fetched and waiting to be executed are completed. When the data storage device exits low power mode, new commands are fetched. The completing and fetching takes time. Rather than completing all of the commands, some selected commands can be stored in a persistent memory region (PMR) when entering low power mode. The storing in PMR is faster than completing the commands. Furthermore, retrieving the commands from PMR is faster than retrieving new commands from a host device on exiting low power mode. Thus, using PMR results in more efficient use of data storage device bandwidth.

Pipeline optimization in low power mode using PMR

Instead of entering lanes into an unused power state, enter unactive lanes into an unconnected power state to save more current during low power states. Using a small control logic will allow a controller to control unactive lanes in low power mode. When a lane is in an unactive power state or in an unused power state, an unactive lane controller (ULC) uses side-band signaling to place the unactive lane into either unused power state or unconnected power state. When a lane is in unused power state, then the ULC places the lane in unconnected power state. A single ULC is able to controller multiple lanes or you can have multiple ULC's, each controlling a single lane.

PHY lanes disabling for power efficiency

A data storage device includes a memory device and a controller coupled to the memory device. When a command is received by the controller from a host device, the controller determines whether the command size is greater than a threshold size. If the command is not greater than the threshold size, the command is sent to a first queue, otherwise, the command is sent to a second queue. Commands are executed from the first queue until a command size tracker value, which increases by a size representative of each command executed from the first queue, equals or exceeds a threshold value. When the command size tracker value equals or exceeds the threshold value, a command from the second queue is executed and the command size tracker value decreases by a size representative of the command from the second queue. Completion messages are sent at specific intervals based on the executing.

Write completion pacing for unbalanced command length

Instead of maximizing the possible bandwidth of device, utilize time slice credits (TSC), to ensure bandwidth average over a sliding window. When the average is ensured over a sliding window, the device should not care when the host decides to sample a 100 mSec for example, as the average will always be correct. By utilizing set percentage of predetermined allotment for the average bandwidth requirement, the system can give out credit on a predetermined interval. The credit is given out based on usage and once credit is depleted, data cannot be sent until more credit is accumulated. When data is not sent, the system is given a chance to accumulate credit to increase the amount of data sent. Once credit is at a level high enough to send data the device will send the data, but not at a speed that will surpass the average bandwidth requirement.

Bandwidth averaging in a stochastic system

The present disclosure generally relates improved key-per IO (KIPO) processing for multiple tenants. Rather than when a tenant requests a key change to stop tenants from working, indirect-double-indexing can be used to prevent bandwidth loss in tenants during adaptions for other tenants. When a tenant requests to manipulate the key-index table, the system will keep working. The current key index list will be duplicated. While the duplicated key-index list is manipulated according to the request, all tenants may still work on their current key-index tables until the request is complete. Once the request is complete, the tenant with the request will switch to the new table, while the old table is updated. Once the old table is updated, the tenant will switch to the updated table for continued work. No tenant, including the tenant that makes the request, continues working as the request is completed.

Key-per-IO multiple tenant isolation

Instead of using address translation cache (ATC) to translate addresses for host queues, bypass the ATC and directly use translated addresses. When creating the submission queues (SQ) or completion queues (CQ), the controller receives the untranslated addresses from the host, and the device is responsible for translating the untranslated addresses before accessing the host queues. The host queue pointers will directly use the translated addresses while bypassing the ATC. When bypassing the ATC, different flows can be used such as create queue command flow and invalidate operations. In a create queue command flow, the firmware (FW) performs address translation by interacting with a translation agent (TA) to receive the translated addresses. With an invalidate flow, the controller scans all untranslated addresses provided by the host at the queue creation time and compares the untranslated addresses against the invalidated address.

Address translation service for host queues

A data storage device includes a memory device and a controller coupled to the memory device. When a copy command is received by the controller from a host device, the controller reads the relevant data from one or more first locations of the memory device. The data is the processed by an Rx path, where the data is decoded, decrypted, and verified. Rather than providing the data back to the host device or being made available to the host device, a copy accelerator loops the data from the Rx path to a Tx path, where protection information is generated and added to the data and the data is encrypted and encoded. The data is then programmed back to the memory device in a second location. By using the copy accelerator, a latency associated with performing copy command operations and other data management operations may be decreased.

NVMe copy command acceleration

Instead of the firmware (FW) monitoring for both an overlap read command and a write protected (WP) overlapped write command, the FW can monitor the overlap table only. The controller will receive a read command or an overlap read command. If the command is not an overlap read command, then the controller will process the command normally. If the command is an overlap read command, then the controller will look for the write command that is being overlapped. When passing the write overlap of write protect (WP) into the data path instead of the exception queue, the FW is limited to monitoring the overlap table. As such, when the WP command is completed the entry is removed by the data path. As a result, the FW can limit monitoring to when the data path clears the overlap table.

Write protect HW acceleration

The disclosure relates in some aspects to managing the fetching and execution of commands stored in submission queues. For example, execution of a command may be blocked at a data storage apparatus due to an internal blocking condition (e.g., a large number of commands of a particular type are pending for execution at the data storage device). As another example, execution of a command may be blocked at a data storage apparatus due to an external blocking condition (e.g., a host device may specify that certain commands are to be executed immediately one after another). The disclosure relates in some aspects to controlling how commands are fetched and executed so that commands that cannot be executed by the data storage apparatus in the near future do not prevent other commands (that are not subject to the same blocking condition) from being executed.

Managed fetching and execution of commands from submission queues

Growing community of inventors

Beer Sheva, Israel

Shay Benisty