Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Westem Digital Technologies, Inc.

Shay Benisty

Ariel Navon

Yehuda Hahn

Alexander Bazarsky

Amir Segev

Tal Sharifie

Alon Marcu

Eran Sharon

Elkana Richter

Yair Baram

Karin Inbar

Alex Bazarsky

Ran Zamir

Yoav Weinberg

Leonid Minz

Ishai Ilani

Avichay Haim Hodes

Rajesh Koul

Amir Rozen

Noga Harari Shechter

Idan Alrod

William Bernard Boyle

Daniel Joseph Linnen

David Avraham

Opher Lieber

Nissim Elmaleh

Vitali Linkovsky

Yoseph Hassan

Julian Vlaiko

Eran Erez

Yuri Ryabinin

Itshak Afriat

Michael James

Erez Frank

Klod Assulin

Tomer Geron

Stephen Gold

Tomer Tzvi Eliash

Chinnakrishnan Ballapuram

Dudy David Avraham

Dmitry Vaysman

Tomer Eliash

James J Walsh

Scheheresade Virani

Ofir Pele

Yan Dumchin

Girish Desai

David Meyer

Marcus A Carlson

Eran Moshe

Rotem Sela

William Guthrie

Kan Lip Vui

Aki Bleyer

Yuval Yoskovits

Ilya Gusev

Simon Bass

Eran Banani

Yossi Yoseph Hassan

Guruswamy Ganesh

Beniamin Kantor

Yevgeny Zagalsky

Oded Karni

Yevgeny Lazarev

Alexey Martynenko

Adi Blum

Klod Ausslin

Amir Turjeman

Gennady Burdo

Data storage devices configured to exploit generative-adversarial-networks (GANs). The GANs include super-resolution GANs (SRGANs). In some examples, a GAN-based reconstruction procedure is implemented within a data storage controller to replace or supplement an error correction coding (ECC) decoding procedure. In other examples, soft bit information is exploited using GANs during decoding. A dissimilarity matrix may be generated to represent differences between an initial image and a GAN-reconstructed image, with matrix values mapped into low-density parity check (LDPC) codewords to facilitate LDPC decoding of data. In still other examples, confidence information obtained from a GAN is incorporated into image pixels. In some examples, GAN reconstruction of data is limited to modifying valley bits. Multiple GANs may be used in parallel with their outcome aggregated.

Data storage device configured for use with a generative-adversarial-network (GAN)

A data storage device and method for device-initiated hibernation are provided. In one embodiment, the data storage device comprises a non-volatile memory and a controller. The controller is configured to: receive, from a host during a set-up phase of a hibernation process, a plurality of write commands with a current state of a volatile memory in the host; store the plurality of write commands in a queue, wherein the plurality of write commands are not executed during the set-up phase of the hibernation process; receive a trigger from the host to perform an execution phase of the hibernation process; and in response to receiving the trigger, execute the plurality of write commands to store the current state of the host's volatile memory in the non-volatile memory of the data storage device. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Data storage device and method for device-initiated hibernation

Data storage devices configured to exploit generative-adversarial-networks (GANs). The GANs include super-resolution GANs (SRGANs). In some examples, a GAN-based decoding (reconstruction) procedure is implemented within a data storage controller to replace or supplement an error correction coding (ECC) decoding procedure to permit a reduction in the number of parity bits used while storing the data. In other examples, soft bit information is exploited using GANs during decoding. A dissimilarity matrix may be generated to represent differences between an initial image and a GAN-reconstructed image, with matrix values mapped into low-density parity check (LDPC) codewords to facilitate LDPC decoding of data. In still other examples, confidence information obtained from a GAN is incorporated into image pixels. In some examples, GAN reconstruction of data is limited to modifying valley bits. Multiple GANs may be used in parallel with their outcome aggregated.

The present disclosure generally relates to read and write operations utilizing barrier commands. Using barrier commands and a snapshot of doorbell states of submission queues (SQs), the necessary write commands to perform a read may be identified and executed to reduce any wait time of the host. As such, host delays during reads and writes are reduced. In absence of a barrier command, the host needs to wait for writes to complete before performing a read. When a barrier command is used, the host needs to wait for the barrier command to complete before performing a read. The controller will execute the post barrier reads only after completing the pre-barrier writes. As will be discussed herein, the controller completes the barrier command as soon as a doorbell snapshot is taken even though the pre-barrier writes may not yet be completed.

Fast execution of barrier command

Instead of incorporating a single interface towards the host for transferring data, utilizing a designated write-only storage logging device. The write-only storage logging device can accept sequential streams and automatically overwrite. The controller will read the log material in a secure manner using a different and separate physical connection than the one used for write. The storage device may have LBA ranges that work as write-only as well as other LBA ranges, which are normal (both reads and writes are enabled). Both options will allow for a traditional file system as well as sharing the storage, but will still protect the log areas that would be used for events that should not be read out.

Read-protected storage device with sequential logging

More efficient memory device usage is possible by altering the memory device management. For example, when the full storage capacity of the memory device will not be used, certain portions of the memory device can be shut off and then turned on when the storage capacity is needed. When less capacity is needed, data can be consolidated and certain portions of the memory device can be shut off. Additionally, rather than operating in multilevel cell (MLC) memory, the memory device can start in single level cell (SLC) memory and transition to MLC memory over time. If there is a determination that less memory is needed, the memory device can transition from MLC memory to SLC memory. In so doing, the storage capacity of the memory device is more appropriately utilized.

Adaptive use of multiple channels in a storage device

A Controller Memory Buffer (CMB) caching mechanism can be used for increased CMB performance. Rather than reading data and writing data from the static random access memory (SRAM), data is read from the SRAM. When data is read from the CMB in SRAM there is increase performance, but little space to process both read and write commands. Using a dynamic random access memory (DRAM) for write commands and CMB in SRAM for read commands allows for increased performance. Due to limited space in the SRAM, when the read commands are read from the host, the commands are deleted. This allows for relevant data stored in the SRAM to be used for the next command, but then deleted for the next command to be processed. The increase in performance is allowed, while not using extra SRAM or DRAM.

CMB caching using hybrid SRAM/DRAM data path

Rather than using low power mode since there is no indication of a sleep mode type to the data storage device, the sleep mode type is inferred by the data storage device, or supplied by the host. In so doing, the sleep type communication is improved. After the system returns power to the data storage device, there may be a read workload, depending on the sleep type. The workload is characterized by a low-queue depth (QD) sequential read from a specific area of the storage medium that was written to just prior to shut down. In response to inference or host cue, the data storage device will modify an operation so that data storage device is optimized to the sleep mode type, resulting in improved performance and power consumption.

Optimized power up in storage memory devices

The present disclosure generally relates to improved handling of write commands. The host memory buffer (HMB) or other storage space can be utilized to delay execution of host write commands which will improve write performance in different use cases and will also allow having more concurrent streams than open blocks without impacting write or read performance. Generally, once a write command is received, the write command is revised as a new write command that is logically equivalent to the original write command. The revised write command is moved to the HMB along with the data. In so doing, the write command is coalesced and write command handling is improved.

Write coalescing via HMB to optimize write performance

Contents of the next commands are considered as part of an arbitration between virtual functions (VFs). The device controller will hold the head of the submission queues (SQ) internally. The controller is able to do so by implementing a small first in first out (FIFO) per submission queue. The second arbiter and the main arbiter, which is responsible for the command scheduling, fetches the commands from the internal small FIFO. Using this technique, the second arbiter gains visibility of the next commands that participate in the arbitration since the next commands are held internally and not in host memory.

Fairness and consistency in multi-function nonvolatile memory (NVM) express (NVMe) device (MFND)

The present disclosure generally relates to improved optimization of a cache lookup operation by structuring the write cache buffers differently using a link-list. Rather than executing a read command first and then executing a write command only after the read command is executed, this disclosure suggests reordering the command executions. A device waits before executing the read command giving the opportunity to obtain the overlap write command. The device then reorders the command execution and executes first the write command and then executes the read command by accessing the write cache instead of the NAND. When two write commands need to be executed consecutively, the link-list operation is used. The controller finds the relevant buffer in the cache that is needed and overwrites the buffer with the new data. The new data is then written to the cache without accessing the cache multiple times.

Write buffer linking for easy cache reads

The present disclosure generally relates to more effective utilization of write and read bandwidth in submission queues (SQs). The data storage device treats a SQ as two separate SQs: one write SQ and one read SQ. Rather than a single fetch pointer for the entire SQ, the write SQ has a write fetch pointer (WFP) while the read SQ has a separate read fetch pointer (RFP). So long as the individual pointers are less than a queue pointer (QP), the data storage device can still process commands for either read or write SQ even if the other SQ has run out of credits. In so doing, read and write bandwidths can be effectively utilized.

Bandwidth balancing for a single namespace tenant in multi-function nonvolatile memory express devices

A data storage device includes a controller. The controller is coupled to a host device. The controller is configured to determine a quality of a peripheral component interconnect express (PCIe) link, wherein the quality of the PCIe link is either greater than or less than a threshold quality, and transmit an error notification to the host device via a sideband when the quality of the PCIe link is less than the threshold quality. The sideband is a different communication channel than the PCIe link. The error notification includes additional information regarding events occurring in the data storage device resulting in the quality of the PCIe link.

Content-rich error notification

A data storage device and method for race-based data access in a multiple host memory buffer system are provided. In one embodiment, the data storage device stores data in a plurality of host memory buffers in the host instead of in just the host memory buffer usually associated with the data. To read the data, the data storage device sends read commands to all of the host memory buffers. That way, even if some of the host memory buffers are busy, the data can be returned from another one of the host memory buffers. In future reads in similar workloads, a read command can be sent to the host memory buffer that returned the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Data storage device and method for race-based data access in a multiple host memory buffer system

There is a tradeoff between the amount of power consumption decreased and the latency needed to return a data storage device back to an operational power mode. When the data storage device receives a wake up indication from a host device, a controller of the data storage device initiates a counter in order to determine a host exit latency. Based on the host exit latency, the controller determines a group of low power state entrance actions from a plurality of groups to perform during a next entrance into a firmware active idle state based on an associated completion wake up time and the host exit latency. The controller selects the group whose completion wake up time is closest to the host exit latency and less than or equal to the host exit latency. The controller performs the selected groups low power state entrance actions during a next entrance into the firmware active idle state.

Low power optimization based upon host exit latency

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Beer Sheva, Israel

Shay Benisty