Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Westem Digital Technologies, Inc.

Shay Benisty

Ariel Navon

Yehuda Hahn

Alexander Bazarsky

Amir Segev

Tal Sharifie

Alon Marcu

Eran Sharon

Elkana Richter

Karin Inbar

Yair Baram

Alex Bazarsky

Ran Zamir

Yoav Weinberg

Leonid Minz

Ishai Ilani

Avichay Haim Hodes

Rajesh Koul

Amir Rozen

Noga Harari Shechter

Idan Alrod

William Bernard Boyle

Daniel Joseph Linnen

Opher Lieber

Nissim Elmaleh

Vitali Linkovsky

Yoseph Hassan

Julian Vlaiko

Eran Erez

Yuri Ryabinin

Itshak Afriat

Michael James

Tomer Geron

Erez Frank

Klod Assulin

Dudy David Avraham

Stephen Gold

Tomer Tzvi Eliash

Chinnakrishnan Ballapuram

Dmitry Vaysman

Tomer Eliash

James J Walsh

Scheheresade Virani

Ofir Pele

Yan Dumchin

David Meyer

Girish Desai

Marcus A Carlson

Eran Moshe

William Guthrie

Rotem Sela

Kan Lip Vui

Simon Bass

Eran Banani

Ilya Gusev

Yuval Yoskovits

Aki Bleyer

Yossi Yoseph Hassan

Guruswamy Ganesh

Oded Karni

Yevgeny Zagalsky

Beniamin Kantor

Amir Turjeman

Klod Ausslin

Yevgeny Lazarev

Alexey Martynenko

Gennady Burdo

Adi Blum

Amit Alon

Moshe Karni

Instead of maximizing the possible bandwidth of device, utilize time slice credits (TSC), to ensure bandwidth average over a sliding window. When the average is ensured over a sliding window, the device should not care when the host decides to sample a 100 mSec for example, as the average will always be correct. By utilizing set percentage of predetermined allotment for the average bandwidth requirement, the system can give out credit on a predetermined interval. The credit is given out based on usage and once credit is depleted, data cannot be sent until more credit is accumulated. When data is not sent, the system is given a chance to accumulate credit to increase the amount of data sent. Once credit is at a level high enough to send data the device will send the data, but not at a speed that will surpass the average bandwidth requirement.

Bandwidth averaging in a stochastic system

The present disclosure generally relates improved key-per IO (KIPO) processing for multiple tenants. Rather than when a tenant requests a key change to stop tenants from working, indirect-double-indexing can be used to prevent bandwidth loss in tenants during adaptions for other tenants. When a tenant requests to manipulate the key-index table, the system will keep working. The current key index list will be duplicated. While the duplicated key-index list is manipulated according to the request, all tenants may still work on their current key-index tables until the request is complete. Once the request is complete, the tenant with the request will switch to the new table, while the old table is updated. Once the old table is updated, the tenant will switch to the updated table for continued work. No tenant, including the tenant that makes the request, continues working as the request is completed.

Key-per-IO multiple tenant isolation

Instead of using address translation cache (ATC) to translate addresses for host queues, bypass the ATC and directly use translated addresses. When creating the submission queues (SQ) or completion queues (CQ), the controller receives the untranslated addresses from the host, and the device is responsible for translating the untranslated addresses before accessing the host queues. The host queue pointers will directly use the translated addresses while bypassing the ATC. When bypassing the ATC, different flows can be used such as create queue command flow and invalidate operations. In a create queue command flow, the firmware (FW) performs address translation by interacting with a translation agent (TA) to receive the translated addresses. With an invalidate flow, the controller scans all untranslated addresses provided by the host at the queue creation time and compares the untranslated addresses against the invalidated address.

Address translation service for host queues

A data storage device includes a memory device and a controller coupled to the memory device. When a copy command is received by the controller from a host device, the controller reads the relevant data from one or more first locations of the memory device. The data is the processed by an Rx path, where the data is decoded, decrypted, and verified. Rather than providing the data back to the host device or being made available to the host device, a copy accelerator loops the data from the Rx path to a Tx path, where protection information is generated and added to the data and the data is encrypted and encoded. The data is then programmed back to the memory device in a second location. By using the copy accelerator, a latency associated with performing copy command operations and other data management operations may be decreased.

NVMe copy command acceleration

Instead of the firmware (FW) monitoring for both an overlap read command and a write protected (WP) overlapped write command, the FW can monitor the overlap table only. The controller will receive a read command or an overlap read command. If the command is not an overlap read command, then the controller will process the command normally. If the command is an overlap read command, then the controller will look for the write command that is being overlapped. When passing the write overlap of write protect (WP) into the data path instead of the exception queue, the FW is limited to monitoring the overlap table. As such, when the WP command is completed the entry is removed by the data path. As a result, the FW can limit monitoring to when the data path clears the overlap table.

Write protect HW acceleration

The disclosure relates in some aspects to managing the fetching and execution of commands stored in submission queues. For example, execution of a command may be blocked at a data storage apparatus due to an internal blocking condition (e.g., a large number of commands of a particular type are pending for execution at the data storage device). As another example, execution of a command may be blocked at a data storage apparatus due to an external blocking condition (e.g., a host device may specify that certain commands are to be executed immediately one after another). The disclosure relates in some aspects to controlling how commands are fetched and executed so that commands that cannot be executed by the data storage apparatus in the near future do not prevent other commands (that are not subject to the same blocking condition) from being executed.

Managed fetching and execution of commands from submission queues

In addition to transmitting over the ASIC-NAND bus the legacy long command format, a data storage device will be able to use also a compressed/improved command format. The alternate command's format is hidden from most parts of the NAND. The NAND can have a layer that will translate compressed/non standard commands to the legacy (standard) format for use by the rest of the NAND device's logic, as currently implemented. According to selected command format, the Low Level Flow Sequencer (LLFS) sequence generator and the flash interface module (FIM) will know which format to use in order to encode the command's content for transmission to the NAND by the FIM/ASIC/controller. The command is then executed on the NAND side according to the selected command scheme. Changes will be applied in the device controller on the ASIC side—to encode the command, and on the NAND side—to decode the command according to the selected format. The controller on the ASIC side decides on the desired format and is responsible to sync any format change with the NAND before sending a command in a different format than currently agreed between the controller and the NAND.

Multiple command format interpretation for SSD

The present disclosure generally relates to improved host memory buffer (HMB) segment selection at the initialization phase. Rather than selecting an HMB segment strictly on one parameter, the selection process will consider multiple factors of the HMB segments. Instead of just selecting a HMB segments based on the size of the HMB segment, the data storage device will perform some basic performance measurements on the provided HMB segments before selecting HMB segments. The selection will be based also on the performance results from the various experiments. The experiments are performed in the initialization phase so the performance of the solid state drive (SSD) will not be impacted. The basic experiments include read, write, and mixed operations toward the HMB segments while measuring the performance and QoS.

HMB multi-segment optimal selection

Splitting an address translation cache (ATC) into two portions can reduce costs and maintain efficient retrieval of data. One portion can be disposed in a first location while a second portion can be disposed in a second location distinct from the first location. The first location can be in the controller. The second location can be in a host memory buffer (HMB) or in a memory device separate from the controller. To obtain translated addresses, untranslated addresses can be searched in the first portion and the corresponding translated addresses can be retrieved from the second portion. When invalidating untranslated addresses, the untranslated addresses of the first portion can be deleted without a need to delete corresponding translated addresses in the second portion. To improve ATC storage capacity, grouping of untranslated addresses is possible using most significant bytes (MSBs).

Hybrid address translation cache using DRAM

Instead of an arbitration over the link not considering bursts, a smart scheduler in a solid state drive (SSD) host interface is burst aware. The scheduler considers the type of transactions that are going to be sent over the interface. The scheduler sends the transactions in the most efficient way while maximizing the efficiency over the host DRAM. The schedulers may be calibrated from time to time on-the-fly to find the optimal configurations adapted to the current workload. The scheduler will organize the packets selected by the arbitration module so that the data transfers are sent in a burst of a predetermined sized to the host for optimum performance. For further optimization other packet types are sent in bursts as well.

Burst awareness scheduler over host interface

Embodiments of the present disclosure generally relate to a target device handling overlap write commands. In one embodiment, a target device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes a random accumulated buffer, a sequential accumulated buffer, and an overlap accumulated buffer. The controller is configured to receive a new write command, classify the new write command, and write data associated with the new write command to one of the random accumulated buffer, the sequential accumulated buffer, or the overlap accumulated buffer. Once the overlap accumulated buffer becomes available, the controller first flushes to the non-volatile memory the data in the random accumulated buffer and the sequential accumulated buffer that was received prior in sequence to the data in the overlap accumulated buffer. The controller then flushes the available overlap accumulated buffer, ensuring that new write commands override prior write commands.

Cache write overlap handling

A method and apparatus for systems and methods for digital signal processing (DSP) in a non-volatile memory (NVM) device comprising CMOS coupled to NVM die, of a data storage device. According to certain embodiments, one or more DSP calculations are provided by a controller to the CMOS components of the NVM, that configure one or more memory die to carry out atomic calculations on the data resident on the die. The results of calculations of each die are provided to an output latch for each die, back-propagating data back to the configured calculation portion as needed, otherwise forwarding the results to the controller. The controller aggregates the results of DSP calculations of each die and presents the results to the host system.

Enhanced digital signal processor (DSP) NAND flash

Reducing extra traffic on the PCIe bus by initiating speculative address translation requests and aggregating them with normal address translation request can lead to significantly improved data retrieval performance. This can be achieved by issuing speculative address translation requests based on history or structure of host buffer pointers previously issued by each tenant. If the device controller determines that there is a high-hit rate probability, the controller will coalesce the speculative requests with the normal address translation request. The coalescing may be accomplished by dynamically changing the length field in the address translation request. The controller may also collect statistics of the speculative address translation requests per tenant. If the controller determines that the performance gain for a specific tenant's workload becomes minimal, the speculative request feature is disabled.

Speculative address translation service requests

Data storage devices configured to exploit generative-adversarial-networks (GANs). The GANs include super-resolution GANs (SRGANs). In some examples, a GAN-based reconstruction procedure is implemented within a data storage controller to replace or supplement an error correction coding (ECC) decoding procedure. In other examples, soft bit information is exploited using GANs during decoding. A dissimilarity matrix may be generated to represent differences between an initial image and a GAN-reconstructed image, with matrix values mapped into low-density parity check (LDPC) codewords to facilitate LDPC decoding of data. In still other examples, confidence information obtained from a GAN is incorporated into image pixels. In some examples, GAN reconstruction of data is limited to modifying valley bits. Multiple GANs may be used in parallel with their outcome aggregated.

Data storage device configured for use with a generative-adversarial-network (GAN)

A data storage device and method for device-initiated hibernation are provided. In one embodiment, the data storage device comprises a non-volatile memory and a controller. The controller is configured to: receive, from a host during a set-up phase of a hibernation process, a plurality of write commands with a current state of a volatile memory in the host; store the plurality of write commands in a queue, wherein the plurality of write commands are not executed during the set-up phase of the hibernation process; receive a trigger from the host to perform an execution phase of the hibernation process; and in response to receiving the trigger, execute the plurality of write commands to store the current state of the host's volatile memory in the non-volatile memory of the data storage device. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Data storage device and method for device-initiated hibernation

Growing community of inventors

Beer Sheva, Israel

Shay Benisty