Synopsys, Inc.

International Business Machines Corporation

Shay Aviv

Tom Kolan

Vitali Sokhin

Hillel Mendelson

Wesam Saleem Ibraheem

Hagai Hadad

An example system includes a processor that can receive a queue testing package. The processor can divide a hardware (HW) queue system to be tested into different types of queues. The processor can also generate a test using the different types of queues. The processor can further execute multiple instances of the generated test. The processor can also further compare results of the multiple instances of the test to detect a hardware fault in the hardware queue system.

Testing of hardware queue systems using on device test generation

Embodiments relate to a system, program product, and method for integrating compiler-based testing in post-silicon validation. The method includes generating a test program through a device-under-test (DUT). The method also includes generating a plurality of memory intervals and injecting the plurality of memory intervals into the test program. The method further includes injecting a plurality of compiled test snippets into the test program and executing one or more post-silicon validation tests for the DUT with the test program.

Compiler-based code generation for post-silicon validation

A method, apparatus and a product for utilizing translation tables for testing processors. The method is used for testing a target processor that utilizes different translation tables to translate virtual addresses to physical addresses. The method comprises obtaining a test template that comprises directives to be executed in different contexts, during each of which a different translation table is utilized to translate virtual addresses to physical addresses. The translation tables to be used by the target processor in the different contexts are determined, so that the translation tables overlap, at least in part.

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Haifa, Israel

Shay Aviv