Intel Corporation

Other

Tahoe Research, Ltd.

Santa Clara

Shawna M Liff

Johanna M Swan

Adel A Elsherbini

Aleksandar Aleksov

Feras Eid

Sasha N Oster

Georgios C Dogiamis

Henning Braunisch

Telesphor Kamgaing

Thomas L Sounart

Arun Chandrasekhar

Gerald S Pasdast

Jimin Yao

Brandon M Rawlings

Debendra Mallik

Omkar G Karhade

Kimin Jun

Eric Jin Li

Yoshihiro Tomita

Robert L Sankman

Veronica Aleman Strong

Patrick R Morrow

Krishna Bharath

Javier A Falcon

Joshua Heppner

Amr Elshazly

Valluri Ramana Rao

Ravindranath Vithal Mahajan

Chuan Hu

Richard J Dischler

Baris Bicen

Van H Le

Nitin A Deshpande

Sanka Ganesan

Brennen Karl Mueller

Han Wui Then

Srinivas V Pietambaram

Mauro J Kobrinsky

Zhiguo Qian

William J Lambert

Peter Chang

Mohammad Enamul Kabir

James S Clarke

Paul B Fischer

Vijay K Nair

Javier Soto Gonzalez

Amram Eitan

Bharat P Penmecha

Gregory S Clemons

Sasikanth Manipatruni

Brian S Doyle

Jeanette M Roberts

Kaladhar Radhakrishnan

Amruthavalli Pallavi Alur

Vivek K Singh

Christopher J Nelson

Sri Chaitra J Chavali

Mark Saltas

Zhichao Zhang

Hubert C George

Bruce A Block

Roman Caudillo

Sairam Agraharam

Larry E Mosley

Robert M Nickerson

Rajasekaran Swaminathan

Yikang Deng

Mitul Bharat Modi

Pramod Malatkar

Gaurav Chawla

Julien Sebot

Kinya Ichikawa

Beomseok Choi

Kevin P O'brien

Kyle Yazzie

Jiro Kubota

Ravi Pillarisetty

Min Huang

Kemal Aygun

John Stephen Guzek

Min Suet Lim

John Joseph Browne

Nicole K Thomas

Eng Huat Goh

Randy B Osborne

Pooya Tadayon

Zachary R Yoscovits

James Chris Matayabas, Jr

Dilan Seneviratne

Ravi V Mahajan

Jiun Hann Sir

Sri Chaitra Jyotsna Chavali

Srikant Nekkanty

Sergio Antonio Chan Arguedas

Anup Pancholi

Charles A Gealer

Nadine L Dabby

Aastha Uppal

Nader N Abazarnia

Tejpal Singh

Techniques and mechanisms for mitigating stress on hybrid bonded interfaces in a multi-tier arrangement of integrated circuit (IC) dies. In an embodiment, first dies are bonded at a host die each via a respective one of first hybrid bond interfaces, wherein a second one or more dies are coupled to the host die each via a respective one of the first dies, and via a respective second hybrid bond interface. Stress at one of the hybrid bond interfaces is mitigated by properties of a first dielectric layer that extends to that hybrid bond interface. In another embodiment, stress at a given one of the hybrid bond interfaces is mitigated by properties of a dummy chip—or alternatively, properties of a patterned encapsulation structure—which is formed on the given hybrid bond interface.

Device, method and system to mitigate stress on hybrid bonds in a multi-tier arrangement of chiplets

Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component, embedded in a first dielectric layer, including a surface and one or more side surfaces at least partially encapsulated by a first magnetic conductive material; and a second microelectronic component, embedded in a second dielectric layer on the first dielectric layer, including a surface and one or more side surfaces at least partially encapsulated by a second magnetic conductive material, wherein the second microelectronic component is coupled to the surface of the first microelectronic component by a hybrid bonding region, and wherein the second magnetic conductive material is coupled to the first magnetic conductive material.

Contiguous shield structures in microelectronic assemblies having hybrid bonding

An integrated circuit (IC) device structure, comprising a host chip having a device layer and one or more first metallization levels over adjacent first and second regions of the device layer. The first metallization levels are interconnected to the device layer. An interconnect chiplet is over the first metallization levels within the first region. The interconnect chiplet comprises a plurality of second metallization levels, and a plurality of third metallization levels over the first metallization levels within the second region and adjacent to the interconnect chiplet. At least one of an interconnect feature dimension or composition differs between one of the second metallization levels and an adjacent one of the third metallization levels.

Selective interconnects in back-end-of-line metallization stacks of integrated circuitry

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer, and including a first metallization stack at the first surface; a device layer on the first metallization stack; a second metallization stack on the device layer; and an interconnect on the first surface of the die electrically coupled to the first metallization stack; a conductive pillar in the first layer; and a second die, having a first surface and an opposing second surface, in a second layer on the first layer, wherein the first surface of the second die is coupled to the conductive pillar and to the second surface of the first die by a hybrid bonding region.

Microelectronic assemblies having backside die-to-package interconnects

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Microelectronic assemblies

Embodiments of the present disclosure provide a microelectronic assembly comprising: an integrated circuit (IC) die in a first layer and a plurality of IC dies in a second layer, at least two adjacent IC dies in the plurality being electrically coupled along their proximate edges by the IC die. The first layer and the second layer are electrically and mechanically coupled by interconnects having a pitch of less than 10 micrometers between adjacent interconnects, and the IC die comprises capacitors and voltage regulator circuitry.

Power delivery through capacitor-dies in a multi-layered microelectronic assembly

Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

Ultra-thin, hyper-density semiconductor packages

A micro-light emitting diode (LED) display and a method of fabricating the same. The method includes aligning a display backplane and a source semiconductor wafer with one another. A plurality of backplane contact pads of a first width are fixed to the backplane and include first solder pads thereon with a second width smaller than the first width. The wafer includes thereon a plurality of micro-LEDs, and a plurality of micro-LED contact pads fixed to the micro-LEDs and having a third width smaller than the first width. The method includes: aligning such that at least some of the micro-LED contact pads register with corresponding first solder pads; releasing at least some of the micro-LEDs from the wafer onto corresponding first solder pads; and forming a plurality of second solder pads by melting the corresponding first solder pads. The second solder pads bond the at least some of the micro-LEDs to corresponding ones of the plurality of backplane contact pads, the second solder pads further extending on said corresponding ones of the plurality of backplane contact pads beyond a footprint thereon of said some of the micro-LEDs.

Micro-LED displays including solder structures and methods

Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region including metal contacts that are distributed non-uniformly. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact.

Direct bonding in microelectronic assemblies

Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.

Composite interposer structure and method of providing same

Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die-level interposer having a first surface and an opposing second surface; a first die coupled to the first surface of the die-level interposer by a first hybrid bonding region having a first pitch; a second die coupled to the second surface of the die-level interposer by a second hybrid bonding region having a second pitch different from the first pitch; and a third die coupled to the second surface of the die-level interposer by a third hybrid bonding region having a third pitch different from the first and second pitches.

Microelectronic assemblies having a hybrid bonded interposer for die-to-die fan-out scaling

An apparatus, comprising an Integrated Circuit (IC) package comprising a dielectric, the IC package has a first surface and an opposing second-surface, wherein the first surface is separated from the second surface by a thickness of the IC package, wherein sidewalls extend along a perimeter and through the thickness between the first surface and the second surface, and a structure comprising a frame that extends at least partially along the perimeter of the IC package, wherein the structure extends at least through the thickness of the IC package and inwardly from the sidewalls of the IC package.

Robust mold integrated substrate

Hybrid bonded 3D die stacks with improved thermal performance, related apparatuses, systems, and methods of fabrication are disclosed. Such hybrid bonded 3D die stacks include multiple levels of dies including a level of the 3D die stack with one or more integrated circuit dies and one or more thermal dies both directly bonded to another level of the 3D die stack.

Thermal performance in hybrid bonded 3D die stacks

Growing community of inventors

Scottsdale, AZ, United States of America

Shawna M Liff