Intel Corporation

Other

Tahoe Research, Ltd.

Santa Clara

Shawna M Liff

Johanna M Swan

Adel A Elsherbini

Aleksandar Aleksov

Feras Eid

Sasha N Oster

Georgios C Dogiamis

Henning Braunisch

Telesphor Kamgaing

Thomas L Sounart

Arun Chandrasekhar

Gerald S Pasdast

Jimin Yao

Brandon M Rawlings

Debendra Mallik

Eric Jin Li

Yoshihiro Tomita

Robert L Sankman

Omkar G Karhade

Veronica Aleman Strong

Patrick R Morrow

Kimin Jun

Javier A Falcon

Krishna Bharath

Joshua Heppner

Amr Elshazly

Valluri Ramana Rao

Ravindranath Vithal Mahajan

Chuan Hu

Richard J Dischler

Baris Bicen

Van H Le

Nitin A Deshpande

Sanka Ganesan

Brennen Karl Mueller

Srinivas V Pietambaram

Mauro J Kobrinsky

Zhiguo Qian

Peter Chang

Mohammad Enamul Kabir

James S Clarke

Paul B Fischer

William J Lambert

Vijay K Nair

Javier Soto Gonzalez

Amram Eitan

Bharat P Penmecha

Gregory S Clemons

Sasikanth Manipatruni

Brian S Doyle

Han Wui Then

Jeanette M Roberts

Kaladhar Radhakrishnan

Vivek K Singh

Christopher J Nelson

Sri Chaitra J Chavali

Mark Saltas

Zhichao Zhang

Hubert C George

Bruce A Block

Roman Caudillo

Sairam Agraharam

Larry E Mosley

Amruthavalli Pallavi Alur

Yikang Deng

Pramod Malatkar

Gaurav Chawla

Kinya Ichikawa

Kevin P O'brien

Kyle Yazzie

Jiro Kubota

Ravi Pillarisetty

Kemal Aygun

Min Huang

John Stephen Guzek

Min Suet Lim

Eng Huat Goh

John Joseph Browne

Nicole K Thomas

Randy B Osborne

Pooya Tadayon

Zachary R Yoscovits

James Chris Matayabas, Jr

Rajasekaran Swaminathan

Robert M Nickerson

Dilan Seneviratne

Mitul Bharat Modi

Ravi V Mahajan

Jiun Hann Sir

Sri Chaitra Jyotsna Chavali

Srikant Nekkanty

Sergio Antonio Chan Arguedas

Anup Pancholi

Julien Sebot

Charles A Gealer

Beomseok Choi

Nadine L Dabby

Aastha Uppal

Nader N Abazarnia

Tejpal Singh

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Microelectronic assemblies

Embodiments of the present disclosure provide a microelectronic assembly comprising: an integrated circuit (IC) die in a first layer and a plurality of IC dies in a second layer, at least two adjacent IC dies in the plurality being electrically coupled along their proximate edges by the IC die. The first layer and the second layer are electrically and mechanically coupled by interconnects having a pitch of less than 10 micrometers between adjacent interconnects, and the IC die comprises capacitors and voltage regulator circuitry.

Power delivery through capacitor-dies in a multi-layered microelectronic assembly

Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

Ultra-thin, hyper-density semiconductor packages

A micro-light emitting diode (LED) display and a method of fabricating the same. The method includes aligning a display backplane and a source semiconductor wafer with one another. A plurality of backplane contact pads of a first width are fixed to the backplane and include first solder pads thereon with a second width smaller than the first width. The wafer includes thereon a plurality of micro-LEDs, and a plurality of micro-LED contact pads fixed to the micro-LEDs and having a third width smaller than the first width. The method includes: aligning such that at least some of the micro-LED contact pads register with corresponding first solder pads; releasing at least some of the micro-LEDs from the wafer onto corresponding first solder pads; and forming a plurality of second solder pads by melting the corresponding first solder pads. The second solder pads bond the at least some of the micro-LEDs to corresponding ones of the plurality of backplane contact pads, the second solder pads further extending on said corresponding ones of the plurality of backplane contact pads beyond a footprint thereon of said some of the micro-LEDs.

Micro-LED displays including solder structures and methods

Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region including metal contacts that are distributed non-uniformly. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact.

Direct bonding in microelectronic assemblies

Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.

Composite interposer structure and method of providing same

Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die-level interposer having a first surface and an opposing second surface; a first die coupled to the first surface of the die-level interposer by a first hybrid bonding region having a first pitch; a second die coupled to the second surface of the die-level interposer by a second hybrid bonding region having a second pitch different from the first pitch; and a third die coupled to the second surface of the die-level interposer by a third hybrid bonding region having a third pitch different from the first and second pitches.

Microelectronic assemblies having a hybrid bonded interposer for die-to-die fan-out scaling

An apparatus, comprising an Integrated Circuit (IC) package comprising a dielectric, the IC package has a first surface and an opposing second-surface, wherein the first surface is separated from the second surface by a thickness of the IC package, wherein sidewalls extend along a perimeter and through the thickness between the first surface and the second surface, and a structure comprising a frame that extends at least partially along the perimeter of the IC package, wherein the structure extends at least through the thickness of the IC package and inwardly from the sidewalls of the IC package.

Robust mold integrated substrate

Hybrid bonded 3D die stacks with improved thermal performance, related apparatuses, systems, and methods of fabrication are disclosed. Such hybrid bonded 3D die stacks include multiple levels of dies including a level of the 3D die stack with one or more integrated circuit dies and one or more thermal dies both directly bonded to another level of the 3D die stack.

Thermal performance in hybrid bonded 3D die stacks

An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.

Skip level vias in metallization layers for integrated circuit devices

An integrated circuit (IC) package may be fabricated having an interposer, one or more microfluidic channels through the interposer, a first IC chip attached to a first side of the interposer, and a second IC chip attached to a second side of the interposer, where the first side of the interposer includes first bond pads coupled to first bond pads of the first IC chip, and the second side of the interposer includes second bond pads coupled to first bond pads of the second IC chip. In an embodiment of the present description, a liquid cooled three-dimensional IC (3DIC) package may be formed with the IC package, where at least two IC devices may be stacked with a liquid cooled interposer. In a further embodiment, the liquid cooled 3DIC package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.

Liquid cooled interposer for integrated circuit stack

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

Microelectronic assemblies with communication networks

Growing community of inventors

Scottsdale, AZ, United States of America

Shawna M Liff