Texas Instruments Corporation

Shawn T Walsh

Youngmin Kim

Arturo Simmons

Charles G Roberts

James B Friedmann

Jaideep Mavoori

John E Campbell

Gregory Boyd Shinn

Sue E Crank

Joe G Tran

Ju-Ai Ruan

Michelle L Hartsell

Wayne A Bather

Troy A Yocum

Vikram N Doshi

Byron T Ahlburn

Dong Joo Bae

Somit Joshi

Thomas M Parrill

Der'E Jan

Janice D Makos

Joshua J Robbins

Arun Sivasothy

Michael J McGranaghan

Sue Ellen Cranck

James E Campbell

James B Fredimann

Methods and devices for preventing channeling of dopants during ion implantation are provided. The method includes providing a semiconductor substrate and depositing a sacrificial scattering layer over at least a portion a surface of the substrate, wherein the sacrificial scattering layer includes an amorphous material. The method further includes ion implanting a dopant through the sacrificial scattering layer to within a depth profile in the substrate. Subsequently, the sacrificial scattering layer can be removed such that erosion of the substrate surface is less than one percent of a thickness of the sacrificial scattering layer.

Method of reducing channeling of ion implants using a sacrificial scattering layer

A mixed voltage CMOS process for high reliability and high performance core transistors and input-output transistors with reduced mask steps. A gate stack () is formed over the silicon substrate (). Ion implantation is performed of a first species and a second species to produce the doping profiles () in the input-output transistors.

Tunable sidewall spacer process for CMOS integrated circuits

A method for forming planar isolation structures for integrated circuits. A etch barrier is formed over the isolation fill material and an etch back is performed to remove material above unetched portions of the substrate. The exposed fill material is etched and planarized to form a planar isolation structure.

Shallow trench isolation planarization using self aligned isotropic etch

A method is given for removing excess oxide from active areas after shallow trench isolation, without the use of chemical-mechanical polishing. A nitride mask protects active areas during the etch of isolation trenches. The trenches are filled with oxide, using high density plasma deposition, which simultaneously etches, providing a sloping contour around the isolation trenches. A further layer of nitride is used to provide a cap over the trench which seals to the underlying layer of nitride. The cap layer of nitride receives a patterned etch to remove the cap only over the active areas. This allows a selective etch to remove the excess oxide, which can be followed by a selective etch to remove the nitride layers.

Method for trench isolation of semiconductor devices

A method of forming a poly-silicide gate electrode (102). The polysilicon deposition is broken into two steps. After the first polysilicon layer (102a) is formed, a very thin oxide (102b) is formed thereover. Polysilicon deposition then continues to form a second polysilicon layer (102c). The oxide layer (102b) inhibits grain growth resulting in a smaller grain size for the second polysilicon layer (102c). Prior to silicide formation, a pre-amorphization implant is performed to amorphize the second polysilicon layer (102c) and possibly some of the first polysilicon layer (102a) as well. Titanium is deposited and reacted with the polysilicon layers to form a silicide. The silicide process consumes the interface between polysilicon layers (102a & 102c) and possibly a portion of the first polysilicon layer (102a). The resulting silicide layer has a more uniform sheet resistance.

Stacked poly/amorphous silicon gate giving low sheet resistance silicide

A method of fabricating an infrared detector and the detector comprising providing a semiconductor layer of group II-VI material, providing an electrically insulating layer having vias therethrough at predetermined locations and having a coefficient of thermal expansion which substantially tracks the coefficient of thermal expansion of said layer, securing the semiconductor layer to the insulating layer, forming infrared detector elements on the semiconductor layer and vias through the semiconductor layer aligned with the vias through the insulating layer, securing the combined semiconductor and insulating layers to the surface of a signal processing semiconductor chip and forming electrical interconnects between the detector elements and the chip through the vias. Also, there is provided an attaching agent securing the chip to the insulating layer, the attaching agent being sufficiently strong to retain the attachment during thermal cycling during processing and receiving thermally caused stresses between the chip and the detector elements.

Method of fabricating infrared detectors and the detector

The disclosure relates to a system for protecting HgCdTe and the like MIS arrays from breakdown during fabrication due to electrostatic charge buildup on the array capacitors. This is accomplished by building into the structure a short circuit across the capacitor plates with a fuse region therein that will evaporate when a voltage is placed thereacross which is sufficient to cause evaporation and low enough not to damage the capacitors.

Electrostatic discharge protection using thin nickel fuse

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Richardson, TX, United States of America

Shawn T Walsh