Motorola Corporation

Other

Shawn R McCaslin

Nicholas R Van Bavel

Tim A Williams

A PSD template for an HDSL2 transmission system includes three regions, a full-duplex region for both upstream and downstream transmission, and two half-duplex regions, a first duplex region for containing substantially upstream power and a half-duplex region for containing substantially downstream power.

Transmission spectra for HDSL2 transmission

An in-phase signal is sampled at an input of a first analog-to-digital converter (41), and a quadrature signal is sampled at an input of a second analog-to-digital converter (42). The output of the first analog-to-digital converter (41) is delayed by an amount equal to one, plus an integer number times four, sample periods to provide a delayed in-pahse signal. Then the delayed in-phase signal is added to the quadrature signal to provide a sum signal. Then a tone is detected in the sum signal. In one embodiment, a data processor (32) stores the output of the analog-to-digital converters (41, 42) in memory (34) and processes the data as programmed by microcode (33).

Method and apparatus for improving wideband detection of a tone

A method of detecting a wideband tone, having a nominal frequency but occurring anywhere within a wide range of frequencies, includes a step of bandpass filtering input data. The bandpass-filtered data is used to predict a value of the input data using an algorithm such as least-mean-squares (LMS) adaptive linear prediction. An error signal is provided as a difference between the actual and predicted values of the input data. By computing the power in the error signal, the presence or absence of a tone can be detected, because a tone causes a smaller prediction error and power than other, non-tone processes such as white noise. A high-to-low transition in power represents a start of a tone, whereas a low-to-high transition in power represents an end of a tone. A tone flag signal is provided in response to a predetermined relationship between two power computations, such as a low-to-high transition.

Method and apparatus for detecting a wideband tone

A phase locked loop circuit generates an output clock that is in phase with a reference clock and is frequency jitter compensated at lower frequencies by translating intrinsic jitter frequency from low frequency to a predetermined range of higher frequencies. The phase locked loop circuit utilizes dithering circuitry to control a switched capacitor network in order to reduce the magnitude of the frequency jitter at lower frequencies. A phase detector and a loop filter of the phase locked loop circuit are implemented using digital circuitry. An oscillator of the phase locked loop is an analog oscillator which is digitally controlled and includes the switched capacitor network. Quantization error in the output clock is minimized by switching an LSB weighted capacitor in the oscillator at a frequency established by the dithering circuitry.

Phase locked loop having low-frequency jitter compensation

A transient-error free interpolating decimator utilizes only two comb filters. The decimator has an integrator circuit, which receives a digitized signal at a first clock rate, and a differentiator circuit. The differentiator includes first and second comb filters for down converting the digital signal at the first clock rate to a second clock rate, and for providing sample points at first and second outputs; the differentiator circuit and the integrator circuit comprise a decimation filter. A delay circuit provides coarse sampling phase adjustments by delaying the second clock rate by a predetermined number of first-clock cycles. A counter generates the second clock rate and provides coarse sampling phase adjustments by adding or deleting cycles of the first clock to or form the second clock. A multiplexer circuit swaps the two outputs when necessary to prevent transient errors generated in the differentiators from being observed. An interpolator circuit makes fine sampling phase adjustments by interpolation to provide an output that is transient-error free. The interpolator circuit includes a bypass circuit for bypassing the first output of the multiplexer circuit for preventing transient errors from being observed.

Transient free interpolating decimator

A digital tone detector receives a modulated input signal selectively containing at least one tone signal component. Two demodulator circuits each demodulate the input signal wherein one demodulator circuit operates at the predetermined frequency of the tone and the other demodulator circuit operates at the second harmonic. When the input tone has a low spectral harmonic power, a ratio of the demodulated outputs of the two demodulators reliably detects the presence of the tone in the input signal.

Growing community of inventors

Cedar Creek, TX, United States of America

Shawn R McCaslin